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Abstract: Software pipelining is a widespread technique aimed at finding an instruction-level parallel schedule for loops. Reducing the execution time of each iteration often results in an increasing demand of resources to execute the loop operations and to store variables. This paper presents a new technique to reduce the register requirements in schedules obtained by means of software pipelining approaches. The technique reschedules the instructions inside the schedule and across schedule boundaries.... (Update)
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2: Software pipelining: An effective scheduling technique for VLIW machines (context) - Lam - 1988
BibTeX entry: (Update)
F. S'anchez and J. Cortadella. Reducing register pressure in software pipelining. Technical Report UPCDAC -1997/74, UPC-DAC, November 1997. Available at www.ac.upc.es/homes/fermin. http://citeseer.ist.psu.edu/sanchez97reducing.html More
@misc{ s'anchez97reducing,
author = "F. S'anchez and J. Cortadella",
title = "Reducing register pressure in software pipelining",
text = "F. S'anchez and J. Cortadella. Reducing register pressure in software pipelining.
Technical Report UPCDAC -1997/74, UPC-DAC, November 1997. Available at www.ac.upc.es/homes/fermin.",
year = "1997",
url = "citeseer.ist.psu.edu/sanchez97reducing.html" }
Citations (may not include all citations):353 Software pipelining: An effective scheduling technique for V.. (context) - Lam - 1988
299 Dependence Analysis for Supercomputing (context) - Banerjee - 1989
277 Advanced compiler optimizations for supercomputers (context) - Padua, Wolfe - 1986
216 Register allocation and spilling via graph coloring (context) - Chaitin - 1982
201 Register allocation via coloring (context) - Chaitin, Auslander et al. - 1981
193 Superscalar Microprocessor Design (context) - Johnson - 1990
176 Some scheduling techniques and an easily schedulable horizon.. (context) - Rau, Glaeser - 1981
151 Force-directed scheduling for the behavioral synthesis of AS.. (context) - Paulin, Knight - 1989
119 Instruction-level parallel processing: History (context) - Rau, Fisher - 1993
114 Lifetime-sensitive modulo scheduling - Huff - 1993
108 Coloring heuristics for register allocation (context) - Briggs, Cooper et al. - 1989
84 The complexity of coloring circular arcs and chords (context) - Garey, Johnson et al. - 1980
80 Optimizing synchronous circuitry by retiming (context) - Leiserson, Rose et al. - 1983
79 Automated synthesis of data paths in digital systems (context) - Tsenj, Siewiorek - 1986
70 Integrating register allocation and instruction scheduling f.. (context) - Bradlee, Eggers et al. - 1991
69 Register allocation by priority based coloring (context) - Chow, Hennessy - 1984
69 Register allocation with instruction scheduling - Pinter - 1993
61 Some experiments in local microcode compaction for horizonta.. (context) - Davidson, Landskov et al. - 1981
56 Minimizing register requirements under resourceconstrained r.. - Govindarajan, Altman et al. - 1994
47 REAL: A program for register allocation (context) - Kurdahi, Parker - 1987
46 Hypernode reduction modulo scheduling - LLosa, Valero et al. - 1995
30 High-Level Synthesis for Real Time Digital Signal Processing (context) - Vanhoof, Van Rompaey et al. - 1993
26 Minimum register requirements for a modulo schedule - Eichenberger, Davidson et al. - 1994
16 Reducing the Impact of Register Pressure on Software Pipelin.. - LLosa - 1996
16 Software pipelining with register allocation and spilling - Wang, Krall et al. - 1994
15 Register allocation using cyclic interval graphs: A new appr.. (context) - Hendren, Gao et al. - 1992
13 A mathematical formulation of the loop pipelining problem - Cortadella, Badia et al. - 1995
9 Loop optimization for horizontal microcoded machines (context) - Bodin, Charot - 1990
8 Transfer free register allocation in cyclic data flow graphs (context) - Stok - 1992
8 InSyn: Integrated scheduling for DSP applications (context) - Sharma, Jain - 1993
8 Time-constrained loop pipelining (context) - S'anchez, Cortadella - 1995
7 An efficient microcode compiler for custom DSP-processors (context) - Goossens, Rabaey et al. - 1987
6 Maximum-throughput software pipelining (context) - S'anchez, Cortadella - 1996
6 Resource-constrained software pipelining for high-level synt.. (context) - S'anchez, Cortadella - 1995
5 Register allocation for software pipelining loops (context) - Rau, Lee et al. - 1992
5 Relative location assignment for repetitive schedules (context) - Meerbergen, Lippens et al. - 1993
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