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Abstract: In this article, a denotational definition of synchronous subset of SystemC is proposed. The subset treated includes modules, processes, threads, wait statement, ports and signals. We propose formal model for System C delta delay. Also, we give a complete semantic definition for the language's two-phase scheduler. The proposed semantic can constitute a base for validating the equivalence of synchronous HDL subsets. (Update)
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BibTeX entry: (Update)
@misc{ salem-formal,
author = "Ashraf Salem",
title = "Formal Semantics of Synchronous SystemC",
url = "citeseer.ist.psu.edu/salem03formal.html" }
Citations (may not include all citations):134 The Verilog Hardware Description language (context) - Moorby, Thomas - 2002
84 The Denotational Descriptions of Programming Languages (context) - Gordon - 1979
32 Principles of Programming Languages (context) - Tennent - 1981
18 Formal verification of VHDL Descriptions in the PREVAIL envi.. (context) - Borrione, Pierre et al. - 1992
18 Denotational Semantics (context) - Schmidt - 1988
15 Formal Semantics for VHDL (context) - Kloos, Breuer - 1995
11 Functional Specification of SystemC (context) - Initiative - 2001
8 The Simulation Semantics of SystemC - Mueller, Ruf et al. - 2001
5 A Formalization of VHDL Simulation Cycle (context) - Van Tassel - 1992
3 A simple denotational semantics, Proof theory and a validati.. (context) - Breuer, Fernandez et al.
3 Denotational Semantics of a Synchronous VHDL subset (context) - Borrione, Salem
3 Towards a formal semantics of IEEE Std. VHDL 1076 (context) - Olcoz, Colon - 1993
2 SystemC Version (context) - Initiative - 2001
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