ABSTRACT Gigabit Routing on a Software-exposed Tiled-microprocessor
Abstract:
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we present the design, implementation and evaluation of a continuum of software-based routers on the MIT RAW microprocessor. The routers presented in this paper explore 1) several design choices for mapping the routing functions to the RAW tiles, 2) the role and behavior of RAW on-chip interconnects for transporting and switching packets, and 3) the placement of packet buffers and their interaction with the RAW on-chip networks. Our experiments evaluate the performance benefit of streaming on-chip networks for transporting packet payloads, effect of buffering on the linecards, and the cost of scaling our design. Our software-based routers on RAW can achieve a throughput of 15Gb/sec – an order of magnitude improvement over previous software routers on traditional general-purpose architectures and at least four times faster than Intel’s IXP1200 Network Processor.
Citations
| 424 | The click modular router – Kohler, Morris, et al. - 2000 |
| 107 | Routing lookups in hardware at memory access speeds – Gupta, Lin, et al. - 1998 |
| 82 | Building a robust software-based router using network processors – Spalink, Karlin, et al. - 2001 |
| 36 | Flexible Control of Parallelism in a Multiprocessor PC Router – Chen, Morris - 2001 |
| 26 | Maintaining packet order in two-stage switches – Keslassy, McKeown - 2002 |
| 25 | et al. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams – Taylor - 2004 |
| 5 | On the performance of multithreaded architectures for network processors – Crowley, Fiuczynski, et al. - 2000 |
| 5 | The Raw Processor Specification – Taylor - 2004 |
| 1 | Chuvpilo and Saman Amarasinghe. High-Bandwidth Packet Switching on the Raw General-purpose Architecture – Gleb - 2003 |
| 1 | Shang-Tse Chuang, Sundar Iyer. Practical algorithms for performance guarantees in buffered crossbars – McKeown - 2005 |
