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Abstract: Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The number of instructions that must be processed (including incorrectly predicted ones) will approach 16 or more per cycle. Since memory operations account for about a third of all instructions executed, these systems will have to support multiple data references per cycle. In this paper, we explore reference stream... (Update)
Context of citations to this paper: More
.... To reduce register file port requirements, we propose a banked organization that bears similarities to that proposed for data caches [10, 20] as well as other previously proposed banked register file organizations (discussed in Section 6) Our approach differs from these...
.... bandwidth (or cache ports) is extremely important for a future wide issue processor to achieve its full performance potential [31] 16] [25], 4] For example, for a processor to sustain 10 instructions per cycle (IPC) the memory subsystem should provide a minimum bandwidth...
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9: High-bandwidth data memory systems for superscalar processors (context) - Sohi, Franklin - 1991
7: Improving the accuracy and performance of memory communication through renaming - Tyson, Austin - 1997
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BibTeX entry: (Update)
J. A. Rivers, G. S. Tyson, E. S. Davidson, and T. M. Austin. "On High-Bandwidth Data Cache Design for Multi-Issue Processors," Proc. of the 30th Annual Int'l Symp. on Microarchitecture, pp. 46 -- 56, Dec. 1997. http://citeseer.ist.psu.edu/rivers97highbandwidth.html More
@inproceedings{ rivers97highbandwidth,
author = "Jude A. Rivers and Gary S. Tyson and Edward S. Davidson and Todd M. Austin",
title = "On High-Bandwidth Data Cache Design for Multi-Issue Processors",
booktitle = "International Symposium on Microarchitecture",
pages = "46-56",
year = "1997",
url = "citeseer.ist.psu.edu/rivers97highbandwidth.html" }
Citations (may not include all citations):183 Trace Cache: A Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Bennett et al. - 1996
177 Evaluating Future Microprocessors: the SimpleScalar Tool Set - Burger, Austin - 1997
93 High-Bandwidth Data Memory Systems for Superscalar Processor.. (context) - Sohi, Franklin - 1991
72 Alpha Architecture Handbook (context) - Corporation, MA - 1994
72 Alpha Architecture Handbook (context) - Corporation, MA - 1996
47 Instruction Issue Logic for High-Performance, Interruptible,.. (context) - Sohi - 1990
37 A Fill-Unit Approach to Multiple Instruction Issue - Franklin, Smotherman - 1994
36 Hardware Support for Large Atomic Units in Dynamically Sched.. (context) - Melvin, Shebanow et al. - 1988
27 Decoupled Access/Execute Computer Architectures (context) - Smith - 1982
26 Advanced Performance Features of the 64-bit PA-8000 (context) - Hunt - 1995
26 the Effective Bandwidth of Interleaved Memories in Vector Sy.. (context) - Oed, Lange - 1985
22 Increasing Cache Port Efficiency for Dynamic Superscalar Mic.. (context) - Wilson, Olukotun et al. - 1996
15 One Billion Transistors, One Uniprocessor, One Chip (context) - Patt, Patel et al. - 1997
11 High-Bandwidth Address Translation for Multiple-Issue Proces.. - Austin, Sohi - 1996
7 Data Caches for Superscalar Processors - Juan, Navarro et al. - 1997
3 IBM Regains Performance Lead with Power (context) - Report, No - 1993
3 Intel Boosts Pentium Pro to 200 MHz (context) - Report, No - 1995
3 PA-8500: The Continuing Evolution of the PA-8000 Family (context) - Lesartre, Hunt - 1997
2 Evaluation of a Scalable Decoupled Microprocessor Design - Tyson - 1997
2 Pseudo-Random Interleaved Memory (context) - Rau - 1991
1 R10000 Superscalar Microprocessor (context) - Yeager - 1995
1 Distributed Storage Control Unit for the Hitachi S3800 Multi.. (context) - Kitai, Isobe et al. - 1994
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.eecs.umich.edu/~jrivers/): More
Reducing Conflicts In Direct-Mapped Caches With A.. - Rivers (1996) (Correct)
mlcache: A Flexible Multi-Lateral Cache Simulator - Tam, Rivers, Tyson, Davidson (1998) (Correct)
On Effective Data Supply For Multi-Issue Processors - Rivers (1997) (Correct)
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