Hardware-efficient fair queueing architectures for high-speed networks (1996) [55 citations — 5 self]
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@INPROCEEDINGS{Rexford96hardware-efficientfair,author = {Jennifer L. Rexford and Albert G. Greenberg and Flavio G. Bonomi},
title = {Hardware-efficient fair queueing architectures for high-speed networks},
booktitle = {In Proceedings of INFOCOM},
year = {1996},
pages = {638--646},
publisher = {IEEE}
}
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Abstract:
In emerging communication networks, a single link may carry traffic for thousands of connections with different traffic parameters and quality-of-service requirements. High-speed links, coupled with small packet/cell sizes, require efficient switch architectures that can handle cell arrivals and departures every few microseconds, or faster. This paper presents a collection of self-clocked fair queueing (SCFQ) architectures amenable to efficient hardware implementation in network switches. Exact and approximate implementations of SCFQ efficiently handle a moderate range of connection bandwidth parameters, while hierarchical arbitration schemes scale to a large range of throughput requirements. Simulation experiments demonstrate that these architectures divide link bandwidth fairly on a small time scale, preserving connection bandwidth and burstiness properties.
Citations
| 1409 | A generalized processor sharing approach to flow control in integrated services network – Parekh - 1992 |
| 939 | Analysis and Simulation of a Fair Queueing Algorithm – Demers, Keshav, et al. - 1989 |
| 116 | On packet switches with infinite storage – Nagle - 1987 |
