(Enter summary)
Abstract: Instruction supply is a crucial component of processor
performance. Instruction prefetching has been proposed as
a mechanism to help reduce instruction cache misses, which
in turn can help increase instruction supply to the processor.
In this paper we examine a new instruction prefetch architecture
called Fetch Directed Prefetching, and compare
it to the performance of next-line prefetching and streaming
buffers. This architecture uses a decoupled branch predictor
and instruction cache, so the... (Update)
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BibTeX entry: (Update)
G. Reinman, B. Calder, T. Austin "Fetch Directed Instruction Prefetching," Proceedings of the 32nd Annual Int'l Symposium on Microarchitecture, November 1999, pp. 16-27. http://citeseer.ist.psu.edu/reinman99fetch.html More
@inproceedings{ reinman99fetch,
author = "Glenn Reinman and Brad Calder and Todd M. Austin",
title = "Fetch Directed Instruction Prefetching",
booktitle = "International Symposium on Microarchitecture",
pages = "16-27",
year = "1999",
url = "citeseer.ist.psu.edu/reinman99fetch.html" }
Citations (may not include all citations):
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