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Abstract: We describe an important memory optimization that arises in the presence of aggregate data structures such as arrays and structs in a C/C++ based system design methodology. We present an algorithm for determining an optimized memory layout of such data. Our implementation consists of a pointer analysis and resolution phase, followed by memory layout optimization. Experiments on typical applications from the DSP domain result in up to 44% improvement in memory performance. (Update)
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BibTeX entry: (Update)
@inproceedings{ panda01cacheefficient,
author = "Preeti Ranjan Panda and Luc Sria and Giovanni De Micheli",
title = "Cache-efficient memory layout of aggregate data structures",
booktitle = "{ISSS}",
pages = "101-106",
year = "2001",
url = "citeseer.ist.psu.edu/ranjan01cacheefficient.html" }
Citations (may not include all citations):163 Hardware-software co-synthesis of microcontrollers (context) - Ernst, Henkel et al. - 1994
161 Specification and Design of Embedded Systems (context) - Gajski, Vahid et al. - 1994
82 Co-Synthesis of Hardware and Software for Digital Embedded S.. (context) - Gupta - 1995
42 Allocation of multiport memories for hierarchical data strea.. (context) - Lippens, van Meerbergen et al. - 1993
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25 Memory Issues in Embedded Systems-On-Chip: Optimizations and.. (context) - Panda, Dutt et al. - 1999
23 Memory data organization for improved cache performance in e.. - Panda, Dutt et al. - 1997
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2 Efficient context-sensitive analysis for C programs (context) - Wilson, Lam - 1995
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