Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert Cohn, Josep Larriba-Pey, P. Geoffrey Lowney, Mateo Valero  Home/Search
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Abstract: Commercial applications such as databases and Web servers constitute the most important market segment for high-performance servers. Among these applications, on-line transaction processing (OLTP) workloads provide a challenging set of requirements for system designs since they often exhibit inefficient executions dominated by a large memory stall component. This behavior arises from large instruction and data footprints and high communication miss rates. A number of recent studies have... (Update)
Context of citations to this paper: More
.... to align branches to benefit the underlying fetch architecture and branch predictor [4] Our previous work presents a detailed analysis [25] of the effects of these optimizations, concluding that the improvements on the instruction cache performance are due to an increase in...
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0.5: Impact of Chip-Level Integration on Performance of OLTP.. - Luiz Andr Barroso (2000) (Correct)
0.5: Performance of Database Workloads on Shared-Memory .. - Ranganathan.. (1998) (Correct)
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4: Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching - Rotenberg, Bennett et al. - 1996
3: Spike optimizer alphant executable - Lowney, An et al. - 1997
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BibTeX entry: (Update)
A. Ramirez, L. A. Barroso, K. A. Gharachorloo, R. Cohn, J. Larriba-Pey, P. G. Lowney, M. Valero. Code Layout Optimizations for Transaction Processing Workloads. Proceedings of the 28 th Intl. Symposium on Computer Architecture, pp. 155-164, June 2001 http://citeseer.ist.psu.edu/ramirez01code.html More
@misc{ ramirez01code,
author = "A. Ramirez and L. Barroso and K. Gharachorloo and R. Cohn and J. Larriba-Pey
and P. Lowney and M. Valero",
title = "Code Layout Optimizations for Transaction Processing Workloads",
text = "A. Ramirez, L. A. Barroso, K. A. Gharachorloo, R. Cohn, J. Larriba-Pey,
P. G. Lowney, M. Valero. Code Layout Optimizations for Transaction Processing
Workloads. Proceedings of the 28 th Intl. Symposium on Computer Architecture,
pp. 155-164, June 2001",
year = "2001",
url = "citeseer.ist.psu.edu/ramirez01code.html" }
Citations (may not include all citations):121 Continuous profiling: Where have all the cycles gone - Anderson, Berc et al. - 1997
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107 Achieving high instruction cache performance with an optimiz.. (context) - Hwu, Chang - 1989
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2 Performance of database workloads on shared-memory systems w.. (context) - Rangananthan, Gharachorloo et al. - 1998
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