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Abstract: We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects of several behavioral synthesis tasks like module selection, clock selection, scheduling, and resource sharing on supply voltage and switched capacitance need to be considered simultaneously to fully derive the benefits of design space exploration at the behavior level. Recent work has established the importance of... (Update)
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...entire low power data path (functional units, registers, interconnect, buses, etc. for a given control and data flow graph (CDFG) 3] [5]. However, a more global approach is needed that first identifies where data characteristics have the Manuscript received July 8, 1999;...
...focus on generating an entire low power data path (functional units, registers, interconnect, buses, etc. for a given CDFG [4] 5] [6]. While these techniques are very powerful, the CDFG based techniques are not directly applicable to large systems because of their size...
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BibTeX entry: (Update)
A. Raghunathan and N. K. Jha, "An Iterative Improvement Algorithm for Low Power Data Path Synthesis," Proceedings of the International Conference on CAD, Nov. 1995, pp. 597-602. http://citeseer.ist.psu.edu/raghunathan95iterative.html More
@inproceedings{ raghunathaniterative,
author = "A. Raghunathan and N. K. Jha",
title = "An Iterative Improvement Algorithm for Low Power Data Path Synthesis",
pages = "597--603",
url = "citeseer.ist.psu.edu/raghunathan95iterative.html" }
Citations (may not include all citations):482 Combinatorial Optimization: Algorithms and Complexity (context) - Papadimitriou, Steiglitz - 1982
296 Low-power CMOS digital design - Chandrakasan, Sheng et al. - 1992
65 Architectural Power Analysis: The Dual Bit Type Method (context) - Landmanand, Rabaey - 1995
53 Low-power digital design (context) - Horowitz, Indermaur et al. - 1994
52 Behavioral synthesis for low power (context) - Raghunathan, Jha - 1994
36 Behavioral level power estimation and exploration - Mehra, Rabaey - 1994
28 Overview of the px64 kbit/s video coding standard (context) - Liou - 1991
15 An ILP formulation for low power based on minimizingswitched.. (context) - Raghunathan, Jha - 1995
15 Microarchitectural synthesis of performance-constrained, low.. (context) - Goodby, Orailoglu et al. - 1994
1 Optimizingpowerusing transformations (context) - Chandrakasan - 1995
1 An exact solution methodology for scheduling in a 3D design .. (context) - Chaudhuri, Blythe et al. - 1995
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SBIR Phase I Final Report VHDL Behavioral Synthesis.. - Contractor.. (Correct)
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