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Abstract: The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute regular vectorizable code at a performance level that can not be achieved using either paradigm on its own. We will show that the combination of the two techniques yields very high performance at a low cost and a low complexity: We will show that this architecture can reach a performance equivalent to a superscalar processor that sustained ... (Update)
Context of citations to this paper: More
.... a vector machine uses much fewer instructions than a scalar machine (because each vector instruction specifies multiple operations) [18]. Therefore, using raw IPC as a performance measure would be meaningless. The solution is as follows. First, each program is run to...
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BibTeX entry: (Update)
F. Quintana, R. Espasa and M. Valero. "A Case for Merging the ILP and DLP Paradigms". In 6th Euromicro Workshop on Parallel and Distributed Processing, Madrid, Spain, January 21-23, 1998, pp. 217-224. http://citeseer.ist.psu.edu/quintana98case.html More
@misc{ quintana98case,
author = "F. Quintana and R. Espasa and M. Valero",
title = "A Case for Merging the ILP and DLP Paradigms",
text = "F. Quintana, R. Espasa and M. Valero. A Case for Merging the ILP and DLP
Paradigms. In 6th Euromicro Workshop on Parallel and Distributed Processing,
Madrid, Spain, January 21-23, 1998, pp. 217-224.",
year = "1998",
url = "citeseer.ist.psu.edu/quintana98case.html" }
Citations (may not include all citations):251 Simultaneous multithreading: Maximizing on-chip parallelism - Tullsen, Eggers et al. - 1996
186 Exploiting choice: Instruction fetch and issue on an impleme.. - Tullsen, Eggers et al. - 1995
177 Evaluating Future Microprocessors: the SimpleScalar Tool Set - Burger, Austin et al. - 1996
175 ComplexityEffective Superscalar Processors - Palacharla, Jouppi et al. - 1997
173 Bulldog: a compiler for VLIW architectures (context) - Ellis - 1985
150 An efficient algorithm for exploiting multiple arithmetic un.. (context) - Tomasulo - 1967
136 Superscalar Microprocessor (context) - Yager - 1996
130 A VLIW architecture for a trace scheduling compiler (context) - Colwell, Nix et al. - 1987
101 IEEE Transactions on Parallel and Distributed Systems (context) - Agarwal, in - 1992
74 Instruction Issue Logic for High-Performance (context) - Sohi - 1990
67 An elementary processor architecture with simultaneous instr.. (context) - Hirata, Kimura et al. - 1992
49 The CRAY-1 computer system (context) - Russell - 1978
40 Increasing the number of strides for conflict-free vector ac.. (context) - Valero, Lang et al. - 1992
39 Characterization of Alpha AXP performance using TP and SPEC .. (context) - Cvetanovic, Bhandarkar - 1994
39 A Simulation Study of Decoupled Architecture Computers (context) - Smith, Weiss et al. - 1986
32 A variable instruction stream extension to the VLIW architec.. (context) - Wolfe, Shen - 1991
30 Memory Latency Effects in Decoupled Architectures - Kurian, Hulina et al. - 1994
28 Decoupled vector architectures - Espasa, Valero - 1996
25 Evaluation of multithreaded uniprocessors for commercial app.. (context) - Eickemeyer, Johnson et al. - 1996
19 Out-of-order Vector Architectures - Espasa, Valero et al. - 1996
19 CONVEX Architecture Reference Manual (context) - Press, Texas - 1992
19 VLIW compilation techniques in a superscalar environment (context) - Ebcioglu, Groves et al. - 1994
18 ACM Transactions on Computer Systems (context) - Smith, Execute - 1984
17 System features and early benchmark results (context) - Oed - 1992
16 Dixie: a trace generation system for the C (context) - Espasa, Martorell - 1994
15 Multithreaded vector architectures - Espasa, Valero - 1997
11 model 91: Machine philosophy and instruction handling (context) - Anderson, Sparacio et al. - 1967
10 The design of the microarchitecture of UltraSPARC (context) - Tremblay, Greenley et al. - 1995
9 Performance characterization of the Alpha 21164 microprocess.. - Cvetanovic, Bhandarkar - 1996
7 The parallel processing feature of the NEC SX-3 supercompute.. (context) - Iwaya, Watanabe - 1991
6 Pathlengths of SPEC benchmarks for PA-RISC (context) - McMahan, Lee - 1993
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3 BiCMOS Microprocessor with Dynamic Execution (context) - Colwell, Steck - 1995
2 Advanced Vector Architectures - Espasa - 1997
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