Miodrag Potkonjak, Wayne Wolf  Home/Search
Context Related
| ucla.edu/~miodrag/...onjak_ICCAD95b.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: ucla.edu/~miodrag/papers/ (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Modern applications are often defined as sets of several computational tasks. This paper presents a synthesis algorithm for ASIC implementations which realize multiple computational tasks under hard real-time deadlines. The algorithm analyzes constraints imposed by task sharing as well as the traditional datapath synthesis criteria. In particular, we demonstrated an efficient technique to combine rate-monotonic scheduling, a widely used hard real-time systems scheduling discipline, with... (Update)
Context of citations to this paper: More
.... a solution was proposed for ASIP design, derived from a very similar solution for systems with concurrent processes but without variants [45]. Different tasks with timing requirements were serialized into a single large sequential process which was, then, synthesized such...
.... market pressure to reduce system cost for consumer products has spurred the development of system level synthesis techniques [5] 10] [28]. The developed system synthesis techniques have been focused on task scheduling and resource allocation algorithms [23] and interface...
Cited by: More
Heuristic Techniques for Synthesis of Hard Real-Time DSP .. - Systems Miodrag.. (Correct)
Heterogeneous BISR-approach using System Level Synthesis.. - Inki Hong Miodrag (Correct)
Application-Driven Synthesis of Memory-Intensive.. - Kirovski, Lee.. (1999) (Correct)
Similar documents (at the sentence level):
13.2%: A Methodology and Algorithms for the Design of Hard Real-Time .. - Potkonjak, Wolf (Correct)
Active bibliography (related documents): More All
0.5: System-level Synthesis of Hard Real-Time Application.. - Lee, Potkonjak, Wolf (Correct)
0.2: The MIMOLA Language, Version 4.1 - Bashford, Bieker, Harking, Leupers.. (1994) (Correct)
0.2: Multiobjective Synthesis of Low-Power Real-Time Distributed.. - Dick (2002) (Correct)
Similar documents based on text: More All
0.4: Synthesis of Hard Real-Time Application Specific Systems - Lee, Potkonjak, Wolf (1999) (Correct)
0.3: Methodology for Behavioral Synthesis-based Algorithm-level .. - Potkonjak, Kim, Karri (1997) (Correct)
0.2: Synthesis of Application Specific Programmable Processors - Kim, Karri, Potkonjak (1997) (Correct)
Related documents from co-citation: More All
9: Computers and Intractability: A Guide to the Theory of NP-Completeness (context) - Garey, Johnson - 1979
7: A system-design methodology: Executable-specification refinement (context) - Gajski, Vahid et al. - 1994
7: Hardware-Software Cosynthesis for Digital Systems - GUPTA, MICHELI - 1993
BibTeX entry: (Update)
M. Potkonjak, W.H. Wolf, "Cost Optimization in ASIC implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", ICCAD95, pp. 446-451, 1995. http://citeseer.ist.psu.edu/potkonjak95cost.html More
@inproceedings{ potkonjakcost,
author = "M. Potkonjak and W. Wolf",
title = "Cost Optimization in {ASIC} Implementation of Periodic Hard-Real Time Systems Using Behavioral Synthesis Techniques",
pages = "446--451",
url = "citeseer.ist.psu.edu/potkonjak95cost.html" }
Citations (may not include all citations):1582 Scheduling Algorithms for Multiprogramming in a Hard Real Ti.. - Liu, Layland - 1973
336 The Rate Monotonic Scheduling Algorithms - Exact Characteriz.. (context) - Lehoczky, Sha et al. - 1986
163 Hardwaresoftware co-synthesis for microcontrollers (context) - Ernst, Henkel et al. - 1993
150 Static Scheduling of Synchronous Data Flow Programs for Digi.. (context) - Lee, Messerschmitt - 1987
138 The High-Level Synthesis of Digital Systems (context) - McFarland, Parker et al. - 1990
137 Hardware-software cosynthesis for digital systems - Gupta, De Micheli - 1993
114 Fast Prototyping of Datapath-Intensive Architectures (context) - Rabaey - 1991
107 Optimizing Power Using Transformations - Chandrakasan - 1995
106 Hardware-Software Co-Design of Embedded Systems (context) - Wolf - 1994
82 Real-Time Scheduling Theory and Ada (context) - Sha, Goodenough - 1990
45 Specification Partitioning for System Design (context) - Vahid, Gajski - 1992
36 A method for partitioning UNITY language in hardware and sof.. - Barros, Rosenstiel et al. - 1994
27 Partitioning Before Logic Synthesis (context) - Camposano, Brayton - 1987
19 Codesign of Architecture for Automotive Powertrain Modules (context) - Hu - 1994
13 Architectural Partitioning for System Level Design (context) - Lagnese, Thomas - 1989
12 High Level Synthesis for Reconfigurable Datapath Structures (context) - Guerra, Potkonjak et al. - 1993
12 Integration of MediumThroughput Signal Processing Algorithms.. - Goossens - 1995
10 Computer-Aided Partitioning of Behavioral Hardware Descripti.. (context) - McFarland - 1983
9 Retargetable Assembly Code Generation by Bootstrapping - Leupers, Schednk et al. - 1994
7 Algorithm Selection: A Quantitative Computation Intensive Op.. (context) - Potkonjak, Rabaey - 1994
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.cs.ucla.edu/~miodrag/papers/): More
FPGA Fingerprinting Techniques for Protecting.. - Lach, Mangione-Smith, .. (1998) (Correct)
Analysis of Watermarking Techniques for Graph Coloring Problem - Qu, Potkonjak (1998) (Correct)
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1998) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC