by Montse Peiron, Mateo Valero, Eduard Ayguad, Toms Lang
Journal of VLSI Signal Processing
http://people.ac.upc.es/eduard/papers/paper_e5.ps.gz
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Abstract:
The simultaneous access to several vectors is typical in vector multiprocessors. When these accesses are performed in an asynchronous manner, collisions in the network and the conflicts in the memory modules produce high latencies that reduce the efficiency of the system. In this paper we propose a block-interleaved storage scheme to store streams as well as a synchronized out-of-order access mechanism to the vectors that compose the stream so no access conflicts occur for several families of strides. 1.
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