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Abstract: As IC fabrication capabilities extend down to sub-half-micron, the significance of interconnect delay and power dissipation can no longer be ignored. Existing enhancements to synthesis and physical design tools have not been able to solve the problem. The only remaining alternative is that tradeoffs in logical and physical domains must be addressed in an integrated manner. Vast business opportunities will be lost unless more revolutionary changes to design flow are made. This paper discusses... (Update)
Context of citations to this paper: More
.... as follows: ffl Placement driven synthesis and mapping: One may keep a companion placement during synthesis and technology mapping [29, 30]. For every logic synthesis operation, the companion placement will be updated. Once the cell positions are known, one can use our delay...
Cited by: More
Interconnect Performance Estimation Models for Synthesis and.. - Cong, Pan (1998) (Correct)
Active bibliography (related documents): More All
1.1: An Integrated Logical and Physical Design Flow for Deep.. - Salek, Lou, Pedram (1999) (Correct)
0.5: A New Global Routing Algorithm for FPGAs - Chang, Thakur, Zhu, Wong (1994) (Correct)
0.4: An Exact Solution to Simultaneous Technology Mapping and.. - Lou, Salek, Pedram (1997) (Correct)
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BibTeX entry: (Update)
M. Pedram, "Logical-physical co-design for deep submicron circuits: challenges and solutions," in Proc. Asia and South Pacific Design Automation Conf., pp. 137--142, Feb. 1998. http://citeseer.ist.psu.edu/pedram98logicalphysical.html More
@inproceedings{ pedram98logicalphysical,
author = "Massoud Pedram",
title = "Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial)",
booktitle = "Asia and South Pacific Design Automation Conference",
pages = "137-142",
year = "1998",
url = "citeseer.ist.psu.edu/pedram98logicalphysical.html" }
Citations (may not include all citations):170 National Technology Roadmap for Semiconductors (context) - Association - 1994
83 GORDIAN: VLSI placement by quadratic programming and slicing.. (context) - Kleinhans, Sigl et al. - 1991
26 A polynomial algorithm for the min-cut linear arrangements o.. (context) - Yannakakis - 1985
24 Layout driven technology mapping (context) - Pedram, Bhat - 1991
21 A methodology and algorithms for post-placement delay optimi.. (context) - Kannan, Suaris et al. - 1994
12 Routability driven fanout optimization (context) - Vaishnav, Pedram - 1993
12 DAGON: technology mapping and local optimization (context) - Keutzer - 1987
10 Timing-driven placement in interaction with netlist transfor.. (context) - Stenz, Riess et al. - 1997
10 Layout-driven logic synthesis for FPGAs (context) - Chang, Cheng et al. - 1994
9 Logic clause analysis for delay optimization (context) - Rohfleisch, Wurth et al. - 1995
9 An exact solution to simultaneous technology mapping and lin.. - Lou, Salek et al. - 1996
8 Gate sizing: a general purpose optimization approach - Coudert - 1996
6 Multilevel synthesis minimizing the routing factor (context) - Abouzeid, Sakouti et al. - 1990
5 Optimal floorplan area optimization (context) - Wang, Wong - 1992
4 Minimizing the routing cost during logic extraction (context) - Vaishnav, Pedram - 1995
3 BEAR-FP: a robust framework for floorplanning - Pedram, Kuh - 1992
3 Combining technology mapping and placement for delay optimiz.. (context) - Chen, Tsay et al. - 1993
3 Maple: A simultaneous technology mapping, placement and glob.. (context) - Togawa, Sato et al. - 1994
3 Alleviating routing congestion by combining logic resynthesi.. - Liu, Pan et al. - 1993
2 Routable technology mapping for LUT FPGA's (context) - Bhat, Hill - 1992
1 3-D parasitic extraction for DSM IC design (context) - Dai, Sun - 1997
1 Interconnect design for DSM ICs (context) - Cong, He et al. - 1997
Documents on the same site (http://atrak.usc.edu/~massoud/publications_nocgi.html): More
BEAR-FP: A Robust Framework for Floorplanning - Pedram, Kuh (1992) (Correct)
Estimation of Peak Power Dissipation in VLSI Circuits Using.. - Wu, Qiu, Pedram (Correct)
Capacitive Coupling Noise in High-Speed VLSI Circuits - Heydari, Pedram (Correct)
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