This paper presents an extensive survey of trends in embedded processor use with an emphasis on emerging applications in wireless communication, multimedia, and general telecommunications. We demonstrate the importance of application-specific instructionset processors (ASIP’s) in high-volume, low cost applications. We also examine some of the underlying trends of the applications in which embedded processors are used. This is followed by a description of embedded software development tool requirements. High-performance software compilation emerges as a key requirement. Finally, specific industrial case studies of products in MPEG, videophone, and low-cost digital signal processor (DSP) applications are used to illustrate the architecture design tradeoffs, and highlight specific tool requirements. A companion paper in this issue [1] presents a comprehensive survey of embedded software development tools, focusing mostly on retargetable software compilation. I.
|
3148
|
Computer architecture : a quantitative approach, 3rd ed
– Hennessy, Patterson, et al.
- 2003
|
|
560
|
Trace scheduling: A technique for global microcode compaction
– Fisher
- 1981
|
|
455
|
Software Pipelining, “An Effective Scheduling Technique for VLIW
– Lam
|
|
342
|
Register allocation and spilling via graph coloring
– Chaitin
- 1982
|
|
260
|
Bulldog: A Compiler for VLIW Architectures
– Ellis
- 1985
|
|
245
|
Superscalar Microprocessor Design
– Johnson
- 1991
|
|
162
|
The high level synthesis of digital systems
– McFarland, Parker, et al.
- 1990
|
|
140
|
The Architecture of Pipelined Computers
– Kogge
- 1981
|
|
140
|
The priority-based coloring approach to register allocation
– Chow, Hennessy
- 1990
|
|
113
|
Register allocation via graph coloring
– Briggs
- 1992
|
|
111
|
DSPstone: a DSP-oriented benchmarking methodology
– Zivojnovic, Velarde, et al.
- 1994
|
|
95
|
Code Generation for Embedded Processors
– Marwedel, Goossens, et al.
- 1995
|
|
89
|
Register allocation via hierarchical graph coloring
– Callahan, Koblenz
- 1991
|
|
87
|
The generation of optimal code for arithmetic expressions
– Sethi, Ullman
- 1970
|
|
80
|
Optimal code generation for expression trees
– Aho, Johnson
- 1976
|
|
79
|
Using and porting
– Stallman
- 1989
|
|
61
|
Register allocation with instruction scheduling: a new approach
– Pinter
- 1993
|
|
59
|
Compiler Design
– Wilhelm, Maurer
- 1995
|
|
57
|
Code selection through object code optimization
– Davidson, Fraser
- 1984
|
|
52
|
Computer Structures: Readings and Examples
– Bell, Newell
- 1971
|
|
48
|
A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture
– Ebcioglu, Nakatani
- 1989
|
|
45
|
Optimizing stack frame accesses for processors with restricted addressing modes
– Bartley
- 1992
|
|
44
|
A new method for compiler code generation
– Glanville, Graham
- 1978
|
|
44
|
Time-constrained code compaction for DSPs
– Leupers, Marwedel
- 1997
|
|
44
|
Percolation scheduling: A parallel compilation technique
– Nicolau
- 1985
|
|
44
|
Instruction-set matching and selection for DSP and ASIP code generation
– LIEM, MAY, et al.
- 1994
|
|
43
|
Flexware: A flexible firmware development environment for embedded systems
– Paulin, Liem, et al.
- 1995
|
|
41
|
Optimal code generation for embedded memory nonhomogeneous register architectures
– Araujo, Malik
- 1995
|
|
41
|
Memory Bank and Register Allocation in Software Synthesis for ASIPs
– Sudarsanam, Malik
- 1995
|
|
38
|
Optimal code generation for expression trees: An application of BURS theory
– Pelegri-Llopart, Graham
- 1988
|
|
38
|
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
– Paulin
- 1995
|
|
31
|
Code generation and optimization for embedded digital signal processors
– LIAO
- 1996
|
|
30
|
Algorithm for address assignment in DSP code generation
– Leupers, Marwedel
- 1996
|
|
29
|
Tree-based mapping of algorithms to predefined structures
– Marwedel
- 1993
|
|
26
|
Instruction set processor specifications (ISPS): The notation and its applications
– Barbacci
- 1981
|
|
26
|
Simple and efficient BURS table generation
– Proebsting
- 1992
|
|
24
|
Code generation for a one-register machine
– Bruno, Sethi
- 1976
|
|
23
|
Combined scheduling and data routing for programmable ASIC systems
– Hartmann
- 1992
|
|
21
|
Verification of hardware descriptions by retargetable code generation
– Nowak, Marwedel
- 1989
|
|
21
|
Embedded System Design”, in: Design Automation for Embedded Systems
– Camposano, Wilberg
- 1996
|
|
20
|
A BDD-based frontend for retargetable compilers
– Leupers, Marwedel
- 1995
|
|
17
|
Instruction selection for embedded DSPs with complex instructions
– Leupers, Marwedel
- 1996
|
|
16
|
Phase coupling and constant generation in an optimizing microcode compiler
– Vegdahl
- 1982
|
|
15
|
The ARM RISC Chip, A Programmer's Guide
– Someren, Atack
- 1994
|
|
15
|
Affix Grammar Driven Code Generation
– GANAPATHI, FISCHER
- 1985
|
|
13
|
The Suppression of Compensation Code
– Gross, Ward
- 1990
|
|
13
|
EPICS: A Flexible Approach to Embedded DSP Cores
– Woudsma
- 1994
|
|
12
|
Programmable DSP architectures
– Lee
- 1988
|
|
12
|
A Data Flow Graph Exchange Standard
– Jos, Stok
- 1992
|
|
12
|
Industrial Experience Using Rule-driven Retargetable Code Generation for Multimedia Applications
– Liem, Paulin, et al.
- 1995
|