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Abstract: Technology decomposition and technology mapping are two potential stages for minimizing circuit power during logic synthesis. Since power in CMOS circuits is directly dependent on the extent of circuit switching activity, we present a novel procedure to construct a low-activity circuit structure in the technology decomposition stage. This would result in low-power circuits when mapped. The algorithm uses the transition density as a measure of switching activity and is applicable to both... (Update)
Context of citations to this paper: More
.... The pre optimization consisted of an initial node minimization using SIS[1] followed by a minimal activity decomposition described in [9], and later a mapping to a library (lib2.genlib) Except C432, all circuits were minimized using full set of don t cares. The mapping was...
.... such as laptop computers and cellular phones has made low power circuit design an increasingly important research area [4, 13, 14, 12, 6, 11]. For example, laptop computers have a limited battery life, and so the circuitry in the computer must be designed to dissipate as...
Cited by: More
A Computer-Aided Design Methodology for Low Power Sequential.. - Monteiro (1996) (Correct)
Automated Phase Assignment for the Synthesis of Low Power.. - Patra, Narayanan (1999) (Correct)
Technology-dependent Transformations for Low-power Synthesis - Panda, Najm (1997) (Correct)
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0.2: Post-Mapping Transformations for Low-Power Synthesis - Panda, Najm (Correct)
0.2: Power Minimization in IC Design: Principles and Applications - Pedram (1996) (Correct)
0.1: Using Gate Sizing to Reduce Glitch Power - Jacobs, Berkelaar (1996) (Correct)
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0.3: A Rapid Boolean Technology Mapping applicable to Power.. - Ferreira, Trullemans.. (1997) (Correct)
0.3: Power-Aware Technology Mapping for LUT-Based FPGAs - Jason Anderson And (Correct)
0.2: Implication-Based Gate-level Synthesis for Low-Power - Topics.. (Correct)
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6: Multilevel Logic Synthesis (context) - Brayton, Hachtel et al. - 1990
6: Low-power Digital CMOS Design (context) - Chandrakasan, Sheng et al. - 1992
6: Technology Mapping for Low Power - Tiwari, Ashar et al. - 1993
BibTeX entry: (Update)
R. Panda and F. N. Najm, "Technology Decomposition for Low-Power Synthesis," IEEE Custom Integrated Circuits Conference, May 1995. http://citeseer.ist.psu.edu/panda95technology.html More
@misc{ panda95technology,
author = "R. Panda and F. Najm",
title = "Technology Decomposition for Low-Power Synthesis",
text = "R. Panda and F. N. Najm, Technology Decomposition for Low-Power Synthesis,
IEEE Custom Integrated Circuits Conference, May 1995.",
year = "1995",
url = "citeseer.ist.psu.edu/panda95technology.html" }
Citations (may not include all citations):98 Transition density: A new measure of activity in digital cir.. - Najm - 1993
87 Multilevel Logic Synthesis (context) - Brayton, Hachtel et al. - 1990
80 On average power dissipation and random pattern testability .. (context) - Shen, Ghosh et al. - 1992
60 Statistical Estimation of the Switching Activity in Digital .. - Xakellis, Najm - 1994
50 Technology Decomposition and Mapping Targeting Low Power Dis.. - Tsui, Pedram et al. - 1993
39 Technology Mapping for Low Power - Tiwari, Ashar et al. - 1993
17 Low-Power Driven Technology mapping under Timing Constraints (context) - Lin, de Man - 1993
12 Low-pass filter for computing the transition density in digi.. - Najm - 1994
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://power.csl.uiuc.edu/~najm/pubs.html): More
Computation of Bus Current Variance for Reliability.. - Najm, Hajj, Yang (1989) (Correct)
Towards a High-Level Power Estimation Capability - Najm (1996) (Correct)
A Monte Carlo Approach for Power Estimation - Burch, Najm, Yang, Trick (1993) (Correct)
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