(Enter summary)
Abstract: The performance trade-off between hardware complexity and clock speed in the design
of superscalar microarchitectures is first investigated. Using the results of this trade-off
analysis, the thesis proposes and evaluates two new superscalar microarchitectures
designed with the goal of achieving high performance by reducing complexity. (Update)
Cited by: More
Microarchitecture Evaluation With Floorplanning - And Interconnect Pipelining
(Correct)
A Communication-Centric Approach To Instruction Steering - For Future Clustered
(Correct)
Single Instruction Fetch Does Not Inhibit - Instruction-Level Parallelism..
(Correct)
Similar documents (at the sentence level):
15.8%: Quantifying the Complexity of Superscalar Processors - Palacharla, Jouppi, Smith (1996)
(Correct)
7.5%: Complexity-Effective Superscalar Processors - Palacharla (1997)
(Correct)
Active bibliography (related documents): More All
0.9: Exploiting Idle Floating-Point Resources For Integer.. - Sastry, Palacharla, Smith (1998)
(Correct)
0.7: Loop Optimization Techniques On Multi-Issue Architectures - Kaiser
(Correct)
0.6: Trap-driven Memory Simulation - Uhlig (1995)
(Correct)
Similar documents based on text: More All
0.5: A Quantitative Assessment of Thread-Level Speculation.. - Marcuello, González (1999)
(Correct)
0.4: Value Prediction for Speculative Multithreaded.. - Marcuello, Tubella.. (1999)
(Correct)
0.4: Dynamic Cluster Assignment Mechanisms - Canal, Parcerisa, González (2000)
(Correct)
Related documents from co-citation: More All
35: Multiscalar processors
- Sohi, Breach et al. - 1995
22: superscalar microprocessor (context) - Yeager - 1996
21: Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
- Rotenberg, Bennett et al. - 1996
BibTeX entry: (Update)
Subbarao Palacharla, Norman P. Jouppi and J.E. Smith. "Complexity-Effective Superscalar Processors". In 24th Annual Internacional Symposium on Computer Architecture, Denver, 1997, pp. 206-218. http://citeseer.ist.psu.edu/palacharla97complexityeffective.html More
@inproceedings{ palacharla97complexityeffective,
author = "Subbarao Palacharla and Norman P. Jouppi and James E. Smith",
title = "Complexity-Effective Superscalar Processors",
booktitle = "{ISCA}",
pages = "206-218",
year = "1997",
url = "citeseer.ist.psu.edu/palacharla97complexityeffective.html" }
Citations (may not include all citations):
3972
Introduction to Algorithms (context) - Cormen, Leiserson et al. - 1992
1575
Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1996
866
Techniques and Tools (context) - Aho, Sethi et al. - 1988
407
Trace scheduling: a technique for global microcode compactio.. (context) - Fisher - 1981
269
Multiscalar processors
- Sohi, Breach et al. - 1995
222
MIPS RISC Architecture (context) - Kane, Heinrich - 1992
200
Principles of CMOS VLSI Design (context) - Weste, Eshraghian - 1993
193
Superscalar Microprocessor Design (context) - Johnson - 1991
186
Exploiting choice: Instruction fetch and issue on an impleme..
- Tullsen - 1996
183
Trace cache: a low latency approach to high bandwidth instru..
- Rotenberg, Bennet et al. - 1996
177
Evaluating future microprocessors: the simplescalar tool set
- Burger, Austin et al. - 1996
173
Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1985
170
The national technology roadmap for semiconductors (context) - Association - 1997
157
Limits of control flow on parallelism
- Lam, Wilson - 1992
150
An efficient algorithm for exploiting multiple arithmetic un.. (context) - Tomasulo - 1967
136
superscalar microprocessor (context) - Yeager - 1996
130
A vliw architecture for a trace scheduling compiler (context) - Colwell, Nix et al. - 1988
125
Trace processors
- Rotenberg, Jacobson et al. - 1997
110
Available instruction-level parallelism for superscalar and ..
- Jouppi, Wall - 1989
102
Dynamic speculation and synchronization of data dependences
- Moshovos, Breach et al. - 1997
97
The Architecture of Pipelined Computers (context) - Kogge - 1981
93
High-bandwidth data memory systems for superscalar processor.. (context) - Sohi, Franklin - 1991
89
Digital Integrated Circuits - A Design Perspective (context) - Rabaey - 1996
81
Implementing precise interrupts in pipelined processors (context) - Smith, Pleszkun - 1988
76
Will physical scalability sabotage performance gains
- Matzke - 1997
74
Instruction issue logic for high-performance (context) - Sohi - 1990
72
Alpha Architecture Handbook (context) - Corporation - 1996
70
The expandable split window paradigm for exploiting fine-gra..
- Franklin, Sohi - 1992
67
approach to scientific array processing architectural design.. (context) - An, scientific et al. - 1981
65
Pipe: A vlsi decoupled architecture (context) - Goodman, Hsieh et al. - 1985
65
Interconnect scaling - the real limiter to high performance .. (context) - Bohr - 1995
62
The multicluster architecture: Reducing cycle time through p..
- Farkas, Chow et al. - 1997
58
Dynamic dependency analysis of ordinary programs
- Austin, Sohi - 1992
57
The inhibition of potential parallelism by conditional jumps (context) - Riseman, Foster - 1972
54
Partitioned register files for VLIWs: A preliminary analysis.. (context) - Capitanio, Dutt et al. - 1992
54
Digital 21264 sets new standard (context) - Gwennap - 1996
53
Improving superscalar instruction dispatch and issue by expl..
- Vajapeyam, Mitra - 1997
49
uses decoupled superscalar design (context) - Gwennap - 1995
49
The cray-1 computer system (context) - Russell - 1978
47
Detection and parallel execution of independent instructions (context) - Tjaden, Flynn - 1970
38
The cydra 5 departmental supercomputer: Design philosophies (context) - Rau, Yen et al. - 1989
35
IEEE Transactions on Software Engineering (context) - Weiser - 1984
35
Register file design considerations in dynamically scheduled..
- Farkas, Jouppi et al. - 1996
30
Decoupled accesexecute computer architecture (context) - Decoupled, computer et al. - 1982
29
The powerpc 604 risc microprocessor (context) - Song, Denman et al. - 1995
27
Parallel operation in the control data (context) - Thornton - 1961
27
A superscalar alpha processor with out-of-order execution (context) - Keller - 1996
26
Selective dual path execution
- Heil, Smith - 1996
26
University of Wisconsin-- Madison (context) - Franklin, Architecture - 1993
25
Risc i: A reduced instruction set vlsi computer (context) - Patterson, Sequin - 1981
25
Structured memory access architecture (context) - Pleszkun, Davidson - 1983
24
Department of Computer Science (context) - Fuller, Jones et al. - 1980
22
An investigation of the performance of various dynamic sched.. (context) - Butler, Patt - 1992
21
Pews: A decentralized dynamic scheduler for ilp processing (context) - Kemp, Franklin - 1996
20
mhz superscalar risc microprocessor with out-of-order execut.. (context) - Gieseke - 1997
19
Optimal pipelining in supercomputers (context) - Kunkel, Smith - 1986
17
The effectiveness of decoupling
- Bird, Rawsthorne et al. - 1993
17
Intel's mmx speeds multimedia (context) - Gwennap - 1996
12
Hal reveals multichip sparc processor (context) - Gwennap - 1995
12
Exploiting idle floating-point resources for integer executi..
- Sastry, Palacharla et al. - 1997
11
The hp-pa8000 risc cpu: A high performance out-of-order proc.. (context) - Kumar - 1996
11
A scaling scheme for interconnect in deep-submicron processe.. (context) - Rahmat, Nakagawa et al. - 1995
10
Design and evaluation of a multiscalar processor
- Breach
10
a high performance restricted data flow architecture having .. (context) - Hwu, Patt - 1986
9
ported cmos register file (context) - Jolly, -ns - 1991
8
Journal of Parallel and Distributed Computing (context) - Dubey, Flynn - 1990
8
The best way to design an automatic calculating machine (context) - Wilkes - 1951
7
Introducing the intel i860 64-bit microprocessor (context) - Kohn, Margulis - 1989
7
Technical Report CSLTR (context) - McFarland, Flynn et al. - 1995
7
HSpice User's Manual (context) - Inc - 1987
7
mhz superscalar risc processor circuit design issues (context) - Vasseghi - 1996
6
An enhanced access and cycle time model for onchip caches (context) - Wilton, Jouppi - 1994
6
Transistor model for a synthetic (context) - Johnson, Jouppi - 1990
5
Machine organization of the IBM RISC system/6000 processor (context) - Grohoski - 1990
5
cmos adder in multiple output domino logic (context) - Hwang, Fisher et al. - 1988
5
ns access 512kb cmos ecl sram (context) - Chappell, ns - 1991
5
Planning a Computer System: Project Stretch (context) - Bucholtz - 1962
5
dynamic adder using non-precharge multiplexers and reduced p.. (context) - um - 1995
4
High-Performance CMOS System Design Using Wave Pipelining
- Nowka - 1995
4
mp: The birth of a supercomputer (context) - August, Brost et al. - 1989
4
IEEE Micro (context) - Hsu, the et al. - 1994
3
Why wire delays will no longer scale for vlsi chips (context) - Wilhelm - 1995
3
Design principles for a high-performance system (context) - Schorr - 1971
3
not for risc processors (context) - Gwennap - 1993
3
Hp's palc low cost superscalar pa risc processor (context) - pa, cost et al. - 1993
3
Ultrasparc adds multimedia instructions (context) - Gwennap - 1995
3
The ibm system/360 model 91: Machine philosophy and instruct.. (context) - Anderson, Sparacio et al. - 1967
3
Technical Report DEC WRL Technical Note TN (context) - McFarling, predictors - 1993
2
Keynote speech at the 24th Annual International Symposium on.. (context) - Smith, Not et al. - 1997
2
New paradigms for instruction level parallelism (context) - Smith - 1995
2
Alternate implementations of two-level adaptive training bra.. (context) - Yeh, Patt - 1992
2
Microarchitecture Techniques to Improve the Design of Supers.. (context) - Chamdani - 1995
2
Unpublished Cray Research Report (context) - Cray-, processor - 1979
2
An analytical access time model for onchip cache memories (context) - Wada, Rajan et al. - 1992
2
Tutorial talk at 28th Annual International Symposium on Micr.. (context) - Hinton, processor - 1995
2
Studies in program characteristics and architectural choices.. (context) - Smith, Sohi - 1990
2
Recent trends (context) - Horowitz, Przybylski et al. - 1992
2
Considerations in computer design -- leading up to the contr.. (context) - Thornton - 1963
2
Personal Communication (context) - Yeager - 1997
2
Circuits and microarchitecture for gigahertz vlsi designs (context) - Nowka, Hofstee - 1997
1
Motivations and design approach for a new 64-bit instruction.. (context) - Crawford, Huck - 1997
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.ece.wisc.edu/~jes/papers/): More
Path-Based Next Trace Prediction - Quinn Jacobson (1997)
(Correct)
Vector Instruction Set Support for Conditional Operations - Smith Greg Faanes (2000)
(Correct)
Implementations of Context-Based Value Predictors - Sazeides, Smith (1997)
(Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC