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Abstract: Knowing the worst case execution times #WCETs# for programs are crucial for the design and veri#cation of real-time systems. Modern hardware architectures utilize pipelinedexecution and cache memory for improved performance. We extend an existing execution time analysis technique, the Implicit Path Enumeration Technique #IPET#, to consider these and other modern hardwarearchitecturefeatures. We extend IPET in two stages. First, we annotate the control #ow graph of the program with variables... (Update)
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BibTeX entry: (Update)
G. Ottosson and M. Sjodin. Worst-case execution time analysis for modern hardware architectures. In Proceedings of ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, June 1997. http://citeseer.ist.psu.edu/ottosson97worst.html More
@inproceedings{ ottosson97worstcase,
author = "Greger Ottosson and Mikael Sj{\"o}din",
title = "Worst-Case Execution Time Analysis for Modern Hardware Architectures",
booktitle = "{ACM} {SIGPLAN} 1997 Workshop on Languages, Compilers, and Tools for Real-Time Systems ({LCT}-{RTS}'97)",
year = "1997",
url = "citeseer.ist.psu.edu/ottosson97worst.html" }
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