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Abstract: This paper formulates and shows how to solve the problem of selecting the cache size and depth of cache pipelining that maximizes the performance of a given instruction-set architecture. The solution combines trace-driven architectural simulations and the timing analysis of the physical implementation of the cache. Increasing cache size tends to improve performance but this improvement is limited because cache access time increases with its size. This trade-off results in an optimization... (Update)
Context of citations to this paper: More
...be used to hide these penalties. Olukotun, Mudge and Brown explored various depths of a pipelined cache from a performance perspective [8]. 4 Methodology 4.1 Processor Model For our processor model we use MARS obtained from the University of Michigan a cycle accurate...
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BibTeX entry: (Update)
K. Olukotun, T. N Mudge, and R. B. Brown, "Multilevel optimization of pipelined caches," IEEE Transactions on computer, vol. 46, no. 10, pp. 1093--1997. http://citeseer.ist.psu.edu/olukotun97multilevel.html More
@article{ olukotun97multilevel,
author = "Kunle Olukotun and Trevor N. Mudge and Richard B. Brown",
title = "Multilevel Optimization of Pipelined Caches",
journal = "IEEE Transactions on Computers",
volume = "46",
number = "10",
pages = "1083-1102",
year = "1997",
url = "citeseer.ist.psu.edu/olukotun97multilevel.html" }
Citations (may not include all citations):1575 Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1996
241 A Study of Branch Prediction Strategies (context) - Smith - 1981
222 MIPS RISC Architecture (context) - Kane, Heinrich - 1992
179 and Packaging for VLSI (context) - Bakoglu, Interconnections - 1990
93 Aspects of Cache Memory and Instruction Buffer Performance (context) - Hill - 1987
65 Computer Technology and Architecture: An Evolving Interactio.. (context) - Hennessy, Jouppi
46 Tracing with Pixie (context) - Smith - 1991
40 An Analytical Access Time Model for On-Chip Cache Memories (context) - Wada, Rajan et al. - 1992
31 Comparing Software and Hardware Schemes for Reducing the Cos.. - Hwu, Conte et al. - 1989
18 A Comparative Study of Set Associative Memory Mapping Algori.. (context) - Smith - 1978
17 Reducing the Branch Penalty in Pipelined Processors (context) - Lilja - 1988
17 Cache and Memory Hierarchy Design (context) - Przybylski - 1990
16 MIPS Computer Systems (context) - Languages, Guide - 1988
14 CheckT c and minT c Timing Verification and Optimal Clocking.. (context) - Sakallah, Mudge et al. - 1990
11 Performance Optimization of Pipelined Primary Caches (context) - Olukotun, Mudge et al. - 1992
10 A 2-ns Cycle, 3.8-ns Access 512kb CMOS ECL SRAM with a Fully.. (context) - Chappell, Chappell et al. - 1991
8 Multilevel Optimization in the Design of a HighPerformance G.. (context) - Olukotun, Brown et al. - 1991
8 Implementing a Cache for High-Performance GaAs Microprocesso.. (context) - Olukotun, Mudge et al. - 1991
4 Gallium Arsenide Process Evaluation Based on a RISC Micropro.. - Brown, Upton et al. - 1993
3 Technology-Organization Trade-Offs in the Architecture of a .. (context) - Olukotun - 1991
2 Synthesis and Verification of a GaAs Microprocessor from a V.. (context) - Brown - 1992
2 A Methodology for the Construction of Accurate Timing Macrom.. (context) - Kayssi - 1993
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