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Abstract: During the last 15 years, embedded systems have grown in complexity and performance to rival desktop systems. The architectures of these systems present unique challenges to processor microarchitecture, including instruction encoding and instruction fetch processes. This paper presents new techniques for reducing embedded system code size without reducing functionality. This approach is to extract the pipeline decoder logic for an embedded VLIW processor in software at system development time.... (Update)
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BibTeX entry: (Update)
S. Larin and T. Conte, "Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors", Proceedings of the 32nd Annual International Symposium on Microarchitecture, pp. 82-92, November 1999. http://citeseer.ist.psu.edu/larin99compilerdriven.html More
@inproceedings{ larin99compilerdriven,
author = "S. Y. Larin and T. M. Conte",
title = "Compiler-driven cached code compression schemes for embedded {ILP} processors",
booktitle = "Proceedings: 32nd Annual International Symposium on Microarchitecture: Haifa, Israel, November 16--18, 1999",
publisher = "IEEE Computer Society Press",
address = "1109 Spring Street, Suite 300, Silver Spring, MD 20910, USA",
isbn = "0-7695-0437-X",
pages = "82--92",
year = "1999",
url = "citeseer.ist.psu.edu/larin99compilerdriven.html" }
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