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Abstract: A Leakage-Biased Domino circuit family is proposed that maintains high speed in active mode but which can be rapidly placed into a low-leakage inactive state by using leakage currents themselves to bias internal nodes. A 32-bit Han-Carlson domino adder circuit is used to compare LB-Domino with conventional single and dual Vt domino circuits. For equal delay and noise margin, the LB-Domino technique gives two decades reduction in steady-state leakage energy compared to a dual-Vt technique. (Update)
Context of citations to this paper: More
.... circuits because domino logic has both superior speed and area characteristics as compared to static CMOS logic circuits [1, 10, 13, 16]. We restrict the analysis to the integer FUs because it is these units that are most heavily utilized. Some domino logic designs have...
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BibTeX entry: (Update)
S. Heo and K. Asanovic. Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction. In Symposium on VLSI Circuits, June 2002. http://citeseer.ist.psu.edu/heo02leakagebiased.html More
@misc{ heo02leakagebiased,
author = "S. Heo and K. Asanovic",
title = "Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction",
text = "S. Heo and K. Asanovic. Leakage-Biased Domino Circuits for Dynamic Fine-Grain
Leakage Reduction. In Symposium on VLSI Circuits, June 2002.",
year = "2002",
url = "citeseer.ist.psu.edu/heo02leakagebiased.html" }
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