(Enter summary)
Abstract: We describe a system for simulating and generating accurate tests for bridging faults in
CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing
the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for
accurate test generation for feedback bridging faults via topological analysis of the feedbackinfluenced
region of the faulty circuit. We present a bridging fault simulation strategy superior
to previously published... (Update)
Context of citations to this paper: More
...achieve high defect coverage. In this work we consider logic testing for resistive bridging faults, as compared to prior work on zero ohm bridges [22]. # ### ### ### ### ### ### ### ### ### # # ### #### #### #### #### #### ######## ##### Figure 1. Bridging resistance...
Cited by: More
Resistive Bridge Fault Modeling, Simulation and Test Generation - Sar-Dessai, al.
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Active bibliography (related documents): More All
1.0: Simulation and Test Pattern Generation for Bridge Faults in CMOS ICs - Roth (1994)
(Correct)
0.7: Test Point Insertion For Non-Feedback Bridging Faults - Touba, al. (1996)
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0.7: Bridge Fault Simulation Strategies for CMOS Integrated Circuits - Chess, Larrabee (1993)
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BibTeX entry: (Update)
B. Chess and T. Larrabee, "Logic Testing of Bridging Faults in CMOS Integrated Circuits," IEEE Trans. Computers, vol. 47, no. 3, pp. 338-345, March 1988. http://citeseer.ist.psu.edu/chess96logic.html More
@article{ chess98logic,
author = "Brian Chess and Tracy Larrabee",
title = "Logic Testing of Bridging Faults in {CMOS} Integrated Circuits",
journal = "IEEE Transactions on Computers",
volume = "47",
number = "3",
pages = "338-345",
year = "1998",
url = "citeseer.ist.psu.edu/chess96logic.html" }
Citations (may not include all citations):
113
Test pattern generation using Boolean satisfiability
- Larrabee - 1992
56
Carafe: An inductive fault analysis tool for CMOS VLSI circu..
- Jee - 1991
56
Carafe: An inductive fault analysis tool for CMOS VLSI circu..
- Jee, Ferguson - 1993
33
Inductive fault analysis of MOS integrated circuits (context) - Shen, Maly et al. - 1985
28
Test pattern generation for realistic bridge faults in CMOS ..
- Ferguson, Larrabee - 1991
22
Biased voting: a method for simulating CMOS bridging faults .. (context) - Maxwell, Aitken - 1993
21
A CMOS fault extractor for inductive fault analysis (context) - Ferguson, Shen - 1988
21
Accurate modeling and simulation of bridging faults (context) - Acken, Millman - 1991
20
Fault simulation for structured VLSI (context) - Waicukauski, Eichelberger et al. - 1985
20
Fault model evolution for diagnosis: Accuracy vs precision (context) - Acken, Millman - 1992
19
Testing for bridging faults (context) - Acken - 1983
19
A practical approach to fault simulation and test generation.. (context) - Abramovici, Menon - 1985
18
Physically realistic fault models for analog CMOS neural net.. (context) - Feltham, Maly - 1991
16
Bridge fault simulation strategies for CMOS integrated circu..
- Chess, Larrabee - 1993
16
EPROOFS: a CMOS bridging fault simulator (context) - Greenstein, Patel - 1992
14
An accurate bridging fault test pattern generator (context) - Millman, Garvey - 1991
13
Department of Electrical Engineering (context) - Acken, Fault et al. - 1988
12
Fast and accurate CMOS bridging fault simulation (context) - Rearick, Patel - 1993
11
A neutral netlist of 10 combinatorial benchmark circuits and.. (context) - Brglez, Fujiwara - 1985
10
Testing CMOS logic gates for realistic shorts
- Chess, Freitas et al. - 1994
8
Diagnosis of realistic bridging faults with single stuck-at ..
- Chess, Lavo et al. - 1995
8
IEEE Transactions on Computers (context) - Mei, stuck-at - 1974
4
Generating test patterns for bridge faults in CMOS ICs
- Chess, Larrabee - 1994
1
Limitations in predicting defect level based on stuck-at fau.. (context) - Park, Naivar et al. - 1995
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Diagnosis of Realistic Bridging Faults with Single.. - Chess, Lavo.. (1995)
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Voyeur: Applied graph browsing for test and diagnosis - Russack (1996)
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