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Power Estimation and Optimization at the Logic  (Make Corrections)  
Level Massoud Pedram Department of EE - Systems University of Southern...



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Abstract: This paper describes various approaches for power analysis and minimization at the logic level including, amongst others, pattern-independent probabilistic and symbolic simulation techniques for power estimation and low power techniques for state assignment, logic restructuring, logic decomposition, technology mapping and pin ordering. (Update)

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BibTeX entry:   (Update)

@misc{ pedram-power,
  author = "Level Massoud Pedram",
  title = "Power Estimation and Optimization at the Logic",
  url = "citeseer.ist.psu.edu/747177.html" }
Citations (may not include all citations):
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51   Probabilistic simulation for reliability analysis of CMOS VL.. - Najm, Burch et al. - 1990
50   Technology decomposition and mapping targeting low power dis.. - Tsui, Pedram et al. - 1993
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