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Abstract: This paper describes various approaches for power analysis and minimization at the logic level including, amongst others, pattern-independent probabilistic and symbolic simulation techniques for power estimation and low power techniques for state assignment, logic restructuring, logic decomposition, technology mapping and pin ordering. (Update)
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BibTeX entry: (Update)
@misc{ pedram-power,
author = "Level Massoud Pedram",
title = "Power Estimation and Optimization at the Logic",
url = "citeseer.ist.psu.edu/747177.html" }
Citations (may not include all citations):1726 Graph-based algorithms for Boolean function manipulation - Bryant - 1986
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62 Probabilistic treatment of general combinational networks (context) - Parker, McCluskey - 1975
52 HYPER-LP: A system for power minimization using architectura.. (context) - Chandrakasan, Potkonjak et al. - 1992
51 Probabilistic simulation for reliability analysis of CMOS VL.. - Najm, Burch et al. - 1990
50 Technology decomposition and mapping targeting low power dis.. - Tsui, Pedram et al. - 1993
46 Accurate simulation of power dissipation in VLSI circuits (context) - Kang - 1986
41 NOVA: State assignment of finite state machines for optimal .. (context) - Villa, Sangiovanni-Vincentelli - 1990
[Article contains additional citations not shown here]
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