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Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures (2004)  (Make Corrections)  
Ramadass Nagarajan, et al.



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Abstract: Technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density will increase the number of execution units on a single chip, and decreasing wire transmission speeds will cause long and variable on-chip latencies. These trends will severely limit the two dominant conventional architectures: dynamic issue superscalars, and static placement and issue VLIWs. We present a new execution model in which the hardware and static scheduler ... (Update)

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BibTeX entry:   (Update)

@misc{ nagarajan-static,
  author = "Ramadass Nagarajan and et al.",
  title = "Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures",
  url = "citeseer.ist.psu.edu/article/nagarajan04static.html" }
Citations (may not include all citations):
407   Trace scheduling: A technique for global microcode compactio.. (context) - Fisher - 1981
353   Software pipelining: An effective scheduling technique for V.. (context) - Lam - 1988
320   MediaBench: A tool for evaluating and synthesizing multimedi.. - Lee, Potkonjak et al. - 1997
175   Complexity-effective superscalar processors - Palacharla, Jouppi et al. - 1997
173   Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1986
160   IMPACT: An architectural framework for multiple-instructioni.. - Chang, Mahlke et al. - 1991
158   Effective compiler support for predicated execution using th.. - Mahlke, Lin et al. - 1992
151   Baring it all to software: RAW machines - Waingold, Taylor et al. - 1997
117   Clock rate versus IPC: The end of the road for conventional .. - Agarwal, Hrishikesh et al. - 2000
62   The multicluster architecture: Reducing cycle time through p.. - Farkas, Chow et al. - 1997
59   Very long instruction word architectures and the ELI (context) - Fisher - 1983
43   Integrated predicated and speculative execution in the IMPAC.. - August, Connors et al. - 1998
39   Balanced scheduling: Instruction scheduling when memory late.. - Kerns, Eggers - 1993
38   Parallel processing: A smart compiler and a dumb machine (context) - Fisher, Ellis et al. - 1984
32   Increasing processor performance by implementing deeper pipe.. (context) - Sprangle, Carmean - 2002
32   Dynamically scheduled VLIW processors - Rau - 1993
32   SPEC CPU (context) - Evaluation - 2000
29   Unified assign and schedule: A new approach to scheduling fo.. - Ozer, Banerjia et al. - 1998
27   Treegion scheduling for wideissue processors - Havanki, Banerjia et al. - 1998
21   HPL-PD architecture specification: Version (context) - Kathail, Schlansker et al. - 2000
21   EPIC: Explicitly parallel instruction computing - Schlansker, Rau - 2000
17   The optimal logic depth per pipeline stage is 6 to 8 FO4 inv.. - Hrishikesh, Jouppi et al. - 2002
15   CARS: A new code generation framework for clustered ILP proc.. - Kailas, Ebcioglu et al. - 2001
14   and DLP with the polymorphous TRIPS architecture (context) - Sankaralingam, Nagarajan et al. - 2003
13   High-speed electrical signaling: overview and limitations - Horowitz, Yang et al. - 1998
11   Introducing the IA-64 architecture - Huck, Morris et al. - 2000
10   Control CPR: A branch height reduction optimization for EPIC.. - Schlansker, Mahlke et al. - 1999
5   Scaling to the end of silicon with EDGE architectures (context) - Burger, Keckler et al. - 2004
5   Software and hardware techniques to optimize register file u.. - Zalamea, Llosa et al. - 2001
5   Convergent scheduling - Lee, Puppin et al. - 2002
4   Optimal integrated code generation for clustered VLIW archit.. (context) - Kessler, Bednarski - 2002
4   Load scheduling with profile information - Lindenmaier, McKinley et al. - 2000
3   Optimizing loop performance for clustered VLIW architectures - Qian, Carr et al. - 2002
2   Effective instruction scheduling techniques for an interleav.. (context) - Gibert, Sanchez et al. - 2002

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