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Abstract: Technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density will increase the number of execution units on a single chip, and decreasing wire transmission speeds will cause long and variable on-chip latencies. These trends will severely limit the two dominant conventional architectures: dynamic issue superscalars, and static placement and issue VLIWs. We present a new execution model in which the hardware and static scheduler ... (Update)
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BibTeX entry: (Update)
@misc{ nagarajan-static,
author = "Ramadass Nagarajan and et al.",
title = "Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures",
url = "citeseer.ist.psu.edu/article/nagarajan04static.html" }
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