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Abstract: Growing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the hit time of large on-chip caches a function of a line's physical location within the cache. Consequently, cache access times will become a continuum of latencies rather than a single discrete latency. This nonuniformity can be exploited to provide ... (Update)
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BibTeX entry: (Update)
@misc{ conference-appears,
author = "Th International Conference",
title = "Appears in the Proceedings of the 10",
url = "citeseer.ist.psu.edu/694470.html" }
Citations (may not include all citations):132 The alpha 21264 microprocessor (context) - Kessler - 1999
104 for semiconductors. Semiconductor Industry Association (context) - technology - 1999
95 Signal delay in RC tree networks (context) - Rubinstein, Penfield et al. - 1983
90 Selective cache ways: On-demand cache resource allocation - Albonesi - 1999
76 The future of wires - Horowitz, Ho et al. - 1999
76 Will physical scalability sabotage performance gains - Matzke - 1997
73 Cacti: An enhanced cache access and cycle time model - Wilton, Jouppi - 1996
65 Run-time adaptive cache hierarchy management via reference a.. - Johnson, Hwu - 1997
53 An overview of the SPHINX speech recognition system (context) - Lee, Hon et al. - 1990
52 A modified approach to data cache management - Tyson, Farrens et al. - 1995
41 A data cache with multiple caching strategies tuned to diffe.. (context) - Gonzalez, Aliagas et al. - 1995
35 A comparison of trace-sampling techniques for multi-megabyte.. - Kessler, Hill et al. - 1994
33 Cache operations by MRU change (context) - So, Rechtshaffen - 1988
26 Inexpensive implementations of set-associativity (context) - Kessler, Jooss et al. - 1989
26 A fully associative software-managed cache design (context) - Hallnor, Reinhardt - 2000
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