Alex Aleta, Josep M. Codina, Jesus Sanchez, Antonio Gonzalez  Home/Search
Context Related
| ac.upc.es/pub/repo...CDAC200125.ps.Z Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: ac.upc.es/recerca/repo...index,en (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: This work presents a novel code generation scheme for clustered microarchitectures. The scheme is based on a preliminary cluster assignment phase implemented through graph partitioning techniques and a scheduling phase that integrates register allocation and spill code generation. The graph partitioning scheme is shown to be very effective due to its global view of the whole code while the partition is generated. Results show a significant speedup when compared with previously proposed... (Update)
Similar documents based on text: More All
0.4: Exploiting Pseudo-schedules to Guide Data.. - Aleta, Codina.. (2002) (Correct)
0.3: Modulo Scheduling for a Fully-Distributed Clustered . . . - Sánchez, al. (2000) (Correct)
0.3: Data Locality Analysis of the SPECfp95 - Sanchez, Gonzalez (1998) (Correct)
BibTeX entry: (Update)
A. Aleta, J. M. Codina, J. Sanchez, and A. Gonzalez. GraphPartitioning Based Instruction Scheduling for Clustered Processors. In Proc. of 34th Int. Symp. on Microarchitecture, Dec 2001. http://citeseer.ist.psu.edu/aleta01graphpartitioning.html More
@misc{ aleta01graphpartitioning,
author = "A. Aleta and J. Codina and J. Sanchez and A. Gonzalez",
title = "GraphPartitioning Based Instruction Scheduling for Clustered Processors",
text = "A. Aleta, J. M. Codina, J. Sanchez, and A. Gonzalez. GraphPartitioning
Based Instruction Scheduling for Clustered Processors. In Proc. of 34th
Int. Symp. on Microarchitecture, Dec 2001.",
year = "2001",
url = "citeseer.ist.psu.edu/aleta01graphpartitioning.html" }
Citations (may not include all citations):421 A Linear-Time Heuristic for Improving Network Partitions (context) - Fiduccia, Mattheyses - 1982
353 Software Pipelining: an Effective Scheduling Technique for V.. (context) - Lam
288 A Fast and High Quality Multilevel Scheme for Partitioning I.. - Karypis, Kumar - 1995
176 Some Scheduling Techniques and an Easily Schedulable Horizon.. (context) - Rau, Glaeser - 1981
173 Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1986
150 Iterative Modulo Scheduling: an Algorithm for Software Pipel.. - Rau - 1994
117 Clock Rate versus IPC: The End of the Road for Conventional .. - Agarwal, Hrishikesh et al. - 2000
114 Lifetime-Sensitive Modulo Scheduling - Huff - 1993
76 The Future of Wires - Ho, Mai et al. - 2001
76 Will physical scalability sabotage performance gains - Matzke - 1997
54 Partitioned Register Files for VLIWs: A Preliminary Analysis.. (context) - Capitanio, Dytt et al. - 1992
42 Analysis of Multilevel Graph Partitioning - Karypis, Kumar - 1995
42 Lx: A Technology Platform for Customizable VLIW Embedded Pro.. - Faraboschi, Brown et al. - 2000
42 Stage Scheduling: a Technique to Reduce the Register Require.. - Eichenberger, Davidson - 1995
41 Digital 21264 Sets New Standard (context) - Gwennap - 1996
[Article contains additional citations not shown here]
Documents on the same site (http://www.ac.upc.es/recerca/reports/DAC/2001/index,en.html): More
Analysis and Evaluation of the Multi-Stage Cascaded.. - Santana, Falcón.. (2001) (Correct)
A Cost-Effective Implementation of Multilevel Tiling - Marta Jimnez Jos (2001) (Correct)
Recovery Mechanism for Latency Misprediction - Enric Morancho Jos (2001) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC