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Abstract: Concurrent Embedded Real-Time Software (CERTS) is intrinsically different from traditional, sequential, independent, and temporally unconstrained software. The verification of software is more complex than hardware due to inherent flexibilities (dynamic behavior) that incur a multitude of possible system states. The verification of CERTS is all the more difficult due to its concurrency and embeddedness. The work presented here shows how the complexity of CERTS verification can be reduced... (Update)
Context of citations to this paper: More
...that before scheduling. This approach allows more scalable verification for embedded real time applications as has been emphasized in [27]. 3.5. Generator Generator component of VERTAF is responsible for generating the OO code for an embedded real time application under...
.... synthesis, there are also some recent work on the verification of software in an embedded system such as the Schedule Verify Map method [12], linear hybrid automata techniques [10, 13] and mapping strategy [8] Controller synthesis for plants (also called supervisor synthesis)...
Cited by: More
Automating Formal Modular Verification of Asynchronous.. - Hsiung, Cheng
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Extended Quasi-Static Scheduling for Formal Synthesis and Code.. - Su, Hsiung (2002)
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Formal Synthesis of Real-Time Embedded Software by Time-Memory.. - Hsiung, Gau (2002)
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Active bibliography (related documents): More All
1.1: Formal Synthesis And Control Of Soft Embedded Real-Time Systems - Hsiung (2001)
(Correct)
0.8: Efficient and User-Friendly Verification - Wang, Hsiung (2002)
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0.4: RESS: Real-Time Embedded Software Synthesis and Prototyping .. - Lee, Hsiung, Wu, Su
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0.5: The DFN-CERT Experience: Building up a new CERT within Europe - Kossakowski (1994)
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0.4: ESSP: An Embedded Software Synthesis and Prototyping.. - Lee, Hsiung, Wu, Su
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0.4: Synthesis of Embedded Software Using Free-Choice Petri.. - Sgroi, Lavagno.. (1999)
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Related documents from co-citation: More All
4: Hardware-software timing coverification of distributed embedded systems
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3: Hardware-software timing coverification of concurrent embedded real-time systems (context) - Hsiung - 2000
3: Timing coverification of concurrent embedded real-time systems
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BibTeX entry: (Update)
P.-A. Hsiung. Embedded software verification in hardware-software codesign. Journal of Systems Architecture --- the Euromicro Journal, 46(15):1435--1450, December 2000. http://citeseer.ist.psu.edu/hsiung00embedded.html More
@misc{ hsiung00embedded,
author = "P. Hsiung",
title = "Embedded software verification in hardware-software codesign",
text = "P.-A. Hsiung. Embedded software verification in hardware-software codesign.
Journal of Systems Architecture --- the Euromicro Journal, 46(15):1435--1450,
December 2000.",
year = "2000",
url = "citeseer.ist.psu.edu/hsiung00embedded.html" }
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The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.cs.ccu.edu.tw/~pahsiung/publications/publications.shtml): More
CMAPS: A Cosynthesis Methodology for Application-Oriented.. - Hsiung, Lee, Chen (1998)
(Correct)
Scheduling System Verification - Hsiung, Wang, Kuo (1999)
(Correct)
Iterative Refinement and Condensation for State-graph Construction - Farn Wang (1998)
(Correct)
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