Lizy Kurian John  Home/Search
Context
Related
| www3.oup.co.uk/computer_jo...430138.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: www3.oup.co.uk/computer_journa... (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: this paper, we present two schemes for reducing intervector interference. First, we propose a memory module partitioning technique in which disjoint access sets are created for each of the concurrent vectors. Various properties of the involved address mapping are presented. Then we present an interlaced data placement scheme, where the simultaneously accessed vectors are interlaced and stored in the memory. The performance of the two schemes is evaluated by simulation. It is observed that... (Update)
Similar documents based on text: More All
2.5: Module Partitioning and Interlaced Data Placement.. - Kurian, Choi, Hulina, .. (1994) (Correct)
0.5: A Comparative Evaluation of Software Techniques to Hide Memory.. - Lizy Kurian (1995) (Correct)
0.3: Eliminating Conflicts between Vector Streams in Interleaved .. - Del Corral Llaberia (1995) (Correct)
BibTeX entry: (Update)
@article{ john00data,
author = "Lizy Kurian John",
title = "Data Placement Schemes to Reduce Conflicts in Interleaved Memories",
journal = "The Computer Journal",
volume = "43",
number = "2",
month = "????",
pages = "138--151",
year = "2000",
url = "citeseer.ist.psu.edu/516474.html" }
Citations (may not include all citations):222 MIPS RISC Architecture (context) - Kane - 1989
117 Access and alignment of data in an array processor (context) - Lawrie - 1975
110 Memory bandwidth limitations of future microprocessors - Burger, Goodman et al. - 1996
93 High bandwidth data memory systems for superscalar processor.. (context) - Sohi, Franklin - 1991
40 Increasing the number of strides for conflict free vectors (context) - Valero, Lang et al. - 1992
38 The organization and use of parallel memories (context) - Budnick, Kuck - 1971
33 Vector access performance in parallel memories using a skewe.. (context) - Harper, Jump - 1987
26 the effective bandwidth of interleaved memories in vector pr.. (context) - Oed, Lange - 1985
24 The prime memory system for array access (context) - Lawrie, Vora - 1982
20 A simulation study of the Cray X-MP memory system (context) - Cheung, Smith - 1986
18 High bandwidth interleaved memories for vector processors (context) - Sohi - 1993
15 Latin squares for parallel array access (context) - Kim, Prasanna - 1993
14 Interleaved parallel schemes: improving memory throughput on.. (context) - Seznec, Lenfant - 1992
12 On randomly interleaved memories (context) - Raghavan, Hayes - 1990
12 The Chinese remainder theorem and the prime memory system (context) - Gao - 1993
[Article contains additional citations not shown here]
Documents on the same site (http://www3.oup.co.uk/computer_journal/hdb/Volume_43/Issue_02/): More
Overcoming the Curse of Dimensionality in Clustering by.. - Murtagh, Starck, BERRY (2000) (Correct)
Facing Up to Faults - Randell (2000) (Correct)
Wait-Free Handshaking using Rainbow Coloring - Papatriantafilou, Tsigas (2000) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC