Javier Zalamea, Josep Llosa, Eduard Ayguade, Mateo Valero  Home/Search
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Abstract: Clustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers and functional units are grouped in clusters so that new instructions are needed to move data between them. New aggressive instruction scheduling techniques are required to minimize the negative effect of resource clustering and delays in moving data around. In this paper we... (Update)
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BibTeX entry: (Update)
J. Zalamea, J. Llosa, E. Ayguad'e, and M. Valero, "Modulo scheduling with integrated register spilling for clustered vliw architectures," Tech. Rep. UPC-DAC- http://citeseer.ist.psu.edu/468157.html More
@misc{ zalamea-modulo,
author = "J. Zalamea and J. Llosa and E. Ayguad'e and M. Valero",
title = "Modulo scheduling with integrated register spilling for clustered vliw
architectures",
text = "J. Zalamea, J. Llosa, E. Ayguad'e, and M. Valero, Modulo scheduling with
integrated register spilling for clustered vliw architectures, Tech. Rep.
UPC-DAC-",
url = "citeseer.ist.psu.edu/468157.html" }
Citations (may not include all citations):217 The Perfect Club benchmarks: Effective performance evaluatio.. - Berry, Chen et al. - 1988
176 Some scheduling techniques and an easily schedulable horizon.. (context) - Rau, Glaeser - 1981
173 Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1986
150 Iterative modulo scheduling: An algorithm for software pipel.. - Rau - 1994
149 Software prefetching (context) - Callahan, Kennedy et al. - 1991
114 Lifetime-sensitive modulo scheduling - Huff - 1993
84 Register allocation for software pipelined loops (context) - Rau, Lee et al. - 1992
69 Software pipelining - Allan, Jones et al. - 1995
67 approach to scientific array processing architectural design.. (context) - approach, array et al. - 1981
59 Very long instruction word architectures and the ELI (context) - Fisher - 1983
54 Partitioned register files for VLIWs: A preliminary analysis.. (context) - Capitanio, Dutt et al. - 1992
52 Register organization for media processing - Rixner, Dally et al. - 2000
46 Hypernode reduction modulo scheduling - Llosa, Valero et al. - 1995
46 The Journal of Supercomputing (context) - Dehnert, Towle et al. - 1993
42 Stage scheduling: A technique to reduce the register require.. - Eichenberger, Davidson - 1995
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