Andrew B. Kahng, C.-W. Albert Tsao  Home/Search
Context Related
| ucla.edu/papers/journal/j29.ps ucla.edu/~abk/papers/journal/j29.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: ucla.edu/publications (more) From: ucla.edu/~abk/publications (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: . Academic clock routing research results have tended to achieve only limited direct impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot constraints, obstacle- and legal location-checking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design ... (Update)
Cited by: More
Bounded-Skew Clock and Steiner Routing - Cong, Kahng, Koh, Tsao (1999) (Correct)
UST/DME: A Clock Tree Router For General Skew Constraints - Tsao, Koh (2000) (Correct)
Similar documents (at the sentence level):
18.7%: More Practical Bounded-Skew Clock Routing - Andrew Kahng (1997) (Correct)
Active bibliography (related documents): More All
1.0: Performance Optimization of VLSI Interconnect Layout - Cong, He, Koh, Madden (1996) (Correct)
0.5: Low Power Clock Distribution Using Multiple Voltages And.. - Jatuchai Pangjun And (2002) (Correct)
0.5: Planar-DME: A Single-Layer Zero-Skew Clock Tree Router - Kahng, Tsao (1996) (Correct)
Similar documents based on text: More All
0.3: Chung-Wen Albert Tsao - Ultima Interconnect Technology (Correct)
0.2: Boosting: Min-Cut Placement with Improved Signal Delay - Andrew Kahng Cse (Correct)
0.1: Betweenness Centrality Correlation in Social Networks - Goh Oh Kahng (2003) (Correct)
Related documents from co-citation: More All
2: An Exact Zero-SkewClock Routing Algorithm (context) - Tsay - 1993
2: Minimum Path-Length Equi-Distant Routing (context) - Edahiro - 1992
2: An Efficient Zero-Skew Routing Algorithm (context) - Edahiro - 1994
BibTeX entry: (Update)
A. B. Kahng and C.-W. A. Tsao. Practical bounded-skew clock routing. Journal of VLSI Signal Processing (Special issue on High Performance Clock Distribution Networks), 16(2-3):199--215, June-July 1997. http://citeseer.ist.psu.edu/kahng97practical.html More
@misc{ kahng97practical,
author = "A. Kahng and C. Tsao",
title = "Practical bounded-skew clock routing",
text = "A. B. Kahng and C.-W. A. Tsao. Practical bounded-skew clock routing. Journal
of VLSI Signal Processing (Special issue on High Performance Clock Distribution
Networks), 16(2-3):199--215, June-July 1997.",
year = "1997",
url = "citeseer.ist.psu.edu/kahng97practical.html" }
Citations (may not include all citations):94 Clustering to minimize the maximum intercluster distance (context) - Gonzalez - 1985
53 On Optimal Interconnections for VLSI (context) - Kahng, Robins - 1995
47 Zero skew clock routing with minimum wirelength - Chao, Hsu et al. - 1992
36 Zero skew clock net routing (context) - Chao, Hsu et al. - 1992
35 Zero-skew clock routing trees with minimum wirelength - Boese, Kahng - 1992
34 Constructing the visibility graph for n line segments in o (context) - Welzl - 1985
32 Clock Distribution networks in VLSI Circuits and Systems: A .. (context) - Friedman - 1995
27 A clustering-based optimization algorithm in zero-skew routi.. - Edahiro - 1993
21 Minimum-cost bounded-skew clock routing - Cong, Koh - 1995
20 Bounded-skew clock and steiner routing under elmore delay - Cong, Kahng et al. - 1995
20 Bounded-skew clock and steiner routing under elmore delay - Cong, Kahng et al. - 1995
18 Minimum skew and minimum path length routing in vlsi layout .. (context) - Edahiro - 1991
15 Skew sensitivity minimization of buffered clock tree (context) - Chung, Cheng - 1994
15 Planar-dme: Improved planar zero-skew clock routing with min.. - Kahng, Albert - 1994
11 Low-cost singlelayer clock trees with exact zero elmore dela.. - Kahng, Albert - 1994
10 Visibility-polygon search and euclidean shortest paths (context) - Asano, Guibas et al. - 1995
9 the bounded-skew clock and steiner routing problems - Huang, Kahng et al. - 1995
8 An edgebased heuristic for rectilinear steiner trees (context) - Borah, Owens et al. - 1994
6 Power optimal buffered clock tree design (context) - Vittal, Marek-Sadowska - 1995
3 Planar-dme: A single-layer zero-skew clock tree router - Kahng, Albert - 1996
3 VLSI Clock Net Routing (context) - Tsao - 1996
3 An algorithm for zeroskew clock tree routing with buffer ins.. - Chen, Wong - 1996
1 Skew and delay optimizationfor reliable buffered clock trees (context) - Pullela, Menezes et al. - 1993
1 Geometric embeddings for faster (context) - Alpert, Kahng - 1993
Documents on the same site (http://vlsicad.cs.ucla.edu/publications.html): More
Improving the Quadratic Objective Function in Module Placement - Hagen, Kahng (1992) (Correct)
On Implementation Choices for Iterative Improvement.. - Hagen, Huang, Kahng (1997) (Correct)
A Direct Combination of the Prim and Dijkstra.. - Alpert, Hu, Huang, Kahng (1993) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC