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A New Virtual Memory Implementation for L4/MIPS (1999)  (Make Corrections)  (1 citation)
Cristan Szmajda



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Abstract: This thesis adapts a new data structure, the level and path compressed trie for use as a page table. Path compression is a technique also applied in the guarded page table,used in the present implementation of the L4/MIPS micro-kernel. Level compression is a recent technique which reduces the depth of guarded page tables so that page table look-up in dense address space distributions can potentially be reduced to only one or two array indexing operations. Like hierarchical page tables,... (Update)

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BibTeX entry:   (Update)

Cristan Szmajda. A new virtual memory implementation for L4/MIPS. BE thesis, School of Computer Science and Engineering, University of NSW, Sydney 2052. http://citeseer.ist.psu.edu/szmajda99new.html   More

@misc{ szmajda52new,
  author = "Cristan Szmajda",
  title = "A New Virtual Memory Implementation for L4/MIPS",
  text = "Cristan Szmajda. A new virtual memory implementation for L4/MIPS. BE thesis,
    School of Computer Science and Engineering, University of NSW, Sydney 2052.",
  year = "2052",
  url = "citeseer.ist.psu.edu/szmajda99new.html" }
Citations (may not include all citations):
223   The Art of Computer Programming (context) - Knuth - 1973
223   The Art of Computer Programming (context) - Knuth - 1973
78   PATRICIA --- Practical Algorithm ToRetrieve Information Code.. (context) - Morrison - 1968
60   MIPS RISC Architecture (context) - Kane, Heinrich - 1992
54   Architectural Support for Translation Table Management in La.. (context) - Huck, Hays - 1993
43   Software Prefetching and Caching for Translation Lookaside B.. - Bala, Kaashoek et al. - 1994
35   Lock-Free Linked Lists Using Compare-and-Swap - Valois - 1995
23   Improved Behaviour of Tries by Adaptive Branching - Andersson, Nilsson - 1993
21   Virtual Memory Management in the VAX/VMS Operating System (context) - Levy, Lipman - 1982
20   Use of Super-pages and Sub-blocking in the Address Translati.. (context) - Talluri
16   Control Data STAR-100 Processor Design (context) - Hintz, Tate - 1972
10   Implementation and Performance of the Mungi Single-Address S.. - Heiser, Elphinstone et al. - 1998
9   MIPS: A VLSI Processor Architecture (context) - Hennessy, Jouppi et al. - 1981
8   IDTR and IDTR RISC Processor Hardware User's Manual (context) - Technology, IDT et al. - 1995
7   Dynamic Storage Allocation in the Atlas Computer (context) - Fotheringham - 1961
7   Architecture of the IBM System (context) - ase, Padegs - 1978
7   Virtual to Real Address Translation Using Hashing (context) - Cocke - 1981
5   micro-kernel on Alpha ---Design and Implementation (context) - Schonberg - 1996
5   Implementing a dynamic compressed trie - Nilsson, Tikkanen - 1998
4   School of Computer Science and Engineering (context) - Elphinstone, Heiser et al. - 1997
3   MC68851 Paged Memory Management Unit User's Manual (context) - Incorporated - 1986
3   Page Table Structures for Fine-Grain Virtual Memory - Liedtke - 1994
3   Guarded Page Tables on the MIPS R - Liedtke, Elphinstone - 1995
2   Amethod for the construction of minimum redundancy codes (context) - Huffman - 1952
1   Faster Searching in Tries and Quadtrees ---AnAnalysis of Lev.. (context) - Andersson, Nilsson - 1994
1   Virtual Memory in a 64-bit Micro-kernel - Elphinstone - 1999
1   TLB for Free: In-Cache Translation for a Multi-processor Wor.. (context) - Ritchie - 1985
1   ANew Page Table for 64-bit Address Spaces (context) - Talluri, Hill et al. - 1995
1   Paging Extensions for the Pentium Pro Processor (context) - Collins - 1996
1   kernel Memory Management (context) - Schonberg, Uhlig - 1996
1   MIPS micro-kernel distribution (context) - Elphinstone - 1999
1   ATree-Based Packet Routing Table for Berkeley Unix (context) - Sklower - 1991

Documents on the same site (http://www.cse.unsw.edu.au/~disy/papers/):   More
The Mungi Single-Address-Space Operating System - Heiser, Elphinstone.. (1998)   (Correct)
L4 Reference Manual MIPS R4x00 Version 1.11 - Elphinstone, Heiser, Liedtke (1999)   (Correct)
L4 on Uni- and Multiprocessor Alpha - Potts (1999)   (Correct)

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