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Incremental CAD (2000)  (Make Corrections)  (2 citations)
Olivier Coudert, Jason Cong, et al.



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Abstract: Comprehensive study of incremental algorithms and solutions in the context of CAD tool development is an open area of research with a great deal of potential. Incremental algorithms for synthesis and layout are needed when design undergoes local or incremental change. Often these local changes are made to react to local change in the design, correct local errors or to make local improvements in one or more of the design quality metrics. In this paper we outline fundamental problems in... (Update)

Cited by:   More
Incremental Timing Budget Management in Programmable - Systems Bozorgzadeh Ghiasi   (Correct)

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2.1:   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED.. - Jason Cong Fellow   (Correct)
1.3:   An Interconnect-Centric Design Flow for Nanometer Technologies - Cong (1999)   (Correct)
1.2:   An Implicit Connection Graph Maze Routing Algorithm for ECO.. - Cong, Fang, Khoo (1999)   (Correct)

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0.3:   Design and Analysis of Physical Design Algorithms - Sarrafzadeh, Bozorgzadeh.. (2001)   (Correct)
0.2:   Incremental Physical Design - Jason Cong Computer (2000)   (Correct)
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BibTeX entry:   (Update)

O. Coudert, J. Cong, S. Malik, and M. Sarrafzadeh. " Incremental CAD. In Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp. 236 244, 2000. http://citeseer.ist.psu.edu/coudert00incremental.html   More

@inproceedings{ coudertincremental,
    author = "Olivier Coudert and Jason Cong and Sharad Malik and Majid Sarrafzadeh",
    title = "Incremental {CAD}",
    pages = "236--244",
    url = "citeseer.ist.psu.edu/coudert00incremental.html" }
Citations (may not include all citations):
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80   A new approach to rectangle intersections (context) - Edelsbrunner - 1983
75   Performance optimization of VLSI interconnect layout - Cong, Koh et al. - 1996
59   TILOS: A posynomial programming approach to transistor sizin.. (context) - Fishburn, Dunlop - 1985
53   Buffer placement in distributed RC-tree networks for minimal.. (context) - van Ginneken - 1990
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22   Pathfinder: a negotiation-based performance-driven router fo.. - McMurchie, Ebeling - 1995
20   Logical effort: Designing for speed on the back of an envelo.. (context) - Sproull, Sutherland - 1991
19   Theory and algorithm of localrefinement -based optimization .. - Cong, He - 1999
16   Behavior of Congestion Minimization During Placement (context) - Wang, Sarrafzadeh - 1999
16   Incremental Synthesis (context) - Brand, Drumm et al. - 1994
15   Interconnect layout optimization by simultaneous steiner tre.. - Okamoto, Cong - 1996
14   An interactive maze router with hints (context) - Arnold, Scott - 1988
14   Incremental Physical Design - Cong, Sarrafzadeh - 2000
13   Multi-center Congestion Estimation and Minimization During P.. - Eguro, Wang et al. - 2000
13   DUNE: A multi-layer gridless routing system with wire planni.. - Fang, Cong et al. - 2000
13   Recent advances in VLSI layout (context) - Kuh, Ohtsuki - 1990
12   New algorithms for gate sizing: A comparative study - Manne, Coudert et al. - 1996
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12   Simultaneous routing and buffer insertion with restrictions .. - Zhou, Wong et al. - 1999
12   An implicit connection graph maze routing algorithm for ECO .. - Cong, Fang et al. - 1999
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9   BooleDozer: Logic Synthesis for ASICs (context) - Stok, Kung et al. - 1996
9   Incremental Routing in FPGAs (context) - Emmert, Bhatia - 1998
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7   Simultaneous buffer insertion and non-Hanan optimization for.. - Hu, Sapatnekar - 1999
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3   Incremental Layout Placement Modification Algorithms (context) - Choy, Cheung et al. - 1996
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1   and Prakash Narain (context) - Brand, Drumm et al. - 1994
1   Gate sizing for constrained delay /power/area optimization (context) - Coudert - 1997
1   Mismatches of Incremental Optimizers and Instance Perturbati.. (context) - Kahng, Mantik - 2000
1   A Timing Constrained Incremental Routing Algorithm for Symme.. - Raman, Liu et al. - 1996
1   Layout driven logic restructuring and decomposition (context) - Pedram, Bhat - 1991
1   An Incremental Floorplanner (context) - Crenshaw, Sarrafzadeh et al. - 1999
1   DRAGON2000: A Fast StandardCell Placement Tool (context) - Yang, Wang et al. - 2000
1   Technology mapping for field programmable gate arrays with i.. (context) - Cong, Huang - 2000

Documents on the same site (http://ballade.cs.ucla.edu/~cong/publications.html):   More
On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping - Cong, Ding (1994)   (Correct)
RASP: A General Logic Synthesis System for SRAM-based FPGAs - Cong, Peck, Ding (1996)   (Correct)
Exploiting Signal Flow and Logic Dependency in Standard Cell.. - Cong, Xu (1995)   (Correct)

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