(Enter summary)
Abstract: Lodging a general enough digital
processing element (PE) in each pixel of a CMOS imager
aims at getting a programmable artificial retina (PAR)
that can support fast, compact, low power and low cost
vision. Using original architecture and circuit
techniques, we have designed and operated a 128 128
PAR capable of grey-level image processing and pattern
recognition with not even 50 transistors per PE.
1. INTRODUCTION
As year 2000 approaches, the progress in VLSI CMOS
technology has a growing... (Update)
Context of citations to this paper: More
.... sensors composed of an SIMD 1 array processor with optical input: a tiny processor is embedded in each pixel of a CMOS image sensor [7]. 1. INTRODUCTION Parallelism is nowadays a common way to increase performance both at the circuit and system level. Structures exhibiting...
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BibTeX entry: (Update)
F. Paillet, D. Mercier, and T.M. Bernard. Second generation programmable artificial retina. In Proc. IEEE ASIC Conf., pages 304--309, September 1999. http://citeseer.ist.psu.edu/paillet99second.html More
@misc{ paillet99second,
author = "F. Paillet and D. Mercier and T. Bernard",
title = "Second generation programmable artificial retina",
text = "F. Paillet, D. Mercier, and T.M. Bernard. Second generation programmable
artificial retina. In Proc. IEEE ASIC Conf., pages 304--309, September 1999.",
year = "1999",
url = "citeseer.ist.psu.edu/paillet99second.html" }
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