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Abstract: This paper presents a new compiler algorithm to eliminate invalidation traffic in virtual shared memory using a hybrid distributed invalidation scheme. It aggressively exploits static scheduling and data layout to accurately determine only those instances when invalidation is necessary, thus avoiding the additional read misses of previous schemes. Equations determining precisely what data should be invalidated are presented and followed by the derivation of approximations amenable to compiler... (Update)
Context of citations to this paper: More
...has been completed. The algorithm determines the array sections to be invalidated or made exclusive under the distributed invalidation [7] optimisation for sequential consistency. Current research is extending this algorithm to consider the more general case of non owner...
.... then we can let w(e) 0 (loops could be fused) This situation can appear in some cases when generating code with the owner computes rule [12]. 3.3 Loop fusion with two types and no fusion preventing edges Suppose that G = V; E = F [ F ; T ) is such that T = fS; Pg (only two...
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BibTeX entry: (Update)
M.O'Boyle, R.W. Ford, and A.P. Nisbet. A compiler algorithm to reduce invalidation latency in virtual shared memory systems. In Proceedings of Parallel Architectures and Compilation Techniques, Boston, USA, October 1996. http://citeseer.ist.psu.edu/oboyle96compiler.html More
@inproceedings{ oboyle96compiler,
author = "M. F. P. {O'Boyle} and A. P. Nisbet and R. W. Ford",
title = "A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems",
booktitle = "Proc. of the 1996 Conf. on Parallel Architectures and Compilation Techniques",
pages = "248--257",
year = "1996",
url = "citeseer.ist.psu.edu/oboyle96compiler.html" }
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132 Data flow Analysis of Array and Scalar References - Feautrier - 1991
92 Cooperative Shared Memory: Software and Hardware for Scalabl.. - Hill, Larus et al. - 1993
50 Compiler Directed Cache Management in Multiprocessors (context) - Cheong, Veidenbaum - 1990
45 Gated SSA-Based Demand-Driven Symbolic Analysis for Parallel.. - Tu, Padua - 1995
45 Dynamic Self Invalidation: Reducing Coherence Overhead in Sh.. - Lebeck, Wood - 1995
33 KAP User'sGuide (context) - Inc - 1988
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16 A Compiler Directed Cache Coherence Scheme with Fast and Par.. (context) - Louri, Sung - 1992
16 CacheCoherenceUsing Local Knowledge - Darnell - 1993
7 User-Level VSM Optimisation and its Application - Ford, Nisbet et al. - 1995
4 An Evaluation of a Compiler Optimization for Improving the P.. (context) - Mounes-Toussi, Lilja et al. - 1994
4 Spinning on Coherency: A NewVSM Optimisation for Write-Inval.. - Nisbet, Ford - 1996
3 Evaluation of Compiler Optimisations for Fortran D on MIMD D.. (context) - Hirananadi, Kennedy - 1992
3 Synchronisation Minimisation in a SPMD Execution Model (context) - Kervella, Bodin - 1995
3 Compiler Reduction of Invalidation Traffic in Virtual Shared.. - Ford, Nisbet - 1996
3 A Compiler Algorithm that Reduces Latency in Ownership-Based.. (context) - Skeppstedt, Stenstrom - 1995
2 A Compiler Strategy for SVM, Proc. of Workshop on Lang., Com.. (context) - Bodin, O'Boyle - 1995
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