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Abstract: Integrating several 1-bit processing elements at the sense amplifiers of a standard RAM improves the performance of massively-parallel applications because of the inherent parallelism and high data bandwidth inside the memory chip. However, implementing such a logic-in-memory system on a host computer poses several challenges because of the small bandwidth at the host system buses, and the different data formats used on the two systems. In this thesis, solutions to these system design issues,... (Update)
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BibTeX entry: (Update)
@misc{ nyasulu-system,
author = "Peter M. Nyasulu",
title = "System Design for a Computational-RAM Logic-In-Memory Parallel-Processing
Machine",
url = "citeseer.ist.psu.edu/nyasulu99system.html" }
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Documents on the same site (http://www.doe.carleton.ca/~pnyasulu/eductn.html):
Architecture and Implementation of a Computational RAM.. - Nyasulu, Snelgrove (1998) (Correct)
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