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Abstract: Real defects (e.g., resistive stuck at or bridging faults) in the very large-scale integration (VLSI) circuits cause intermediate voltages which cannot be modeled as ideal shorts. In this paper, we first show that the traditional zero-resistance model is not sufficient for fault simulation. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate level. Our method uses Takagi--Sugeno (TS) fuzzy system... (Update)
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BibTeX entry: (Update)
@misc{ nourani-application,
author = "Mehrdad Nourani and Amir R. Attarha and Caro Lucas",
title = "Application of Fuzzy Logic in Resistive Fault Modeling and Simulation",
url = "citeseer.ist.psu.edu/nourani02application.html" }
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