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Abstract: New BIST methodology for RTL data paths is presented. The proposed BIST methodology takes advantage of the structural information of RTL data path and reduces the test application time by grouping same-type modules into test compatibility classes (TCCs). During testing, compatible modules share a small number of test pattern generators at the same test time leading to significant reductions in BIST area overhead, performance degradation and test application time. Module output responses from... (Update)
Context of citations to this paper: More
.... minimisation techniques for testing low power VLSI circuits at RTL, Chapter 5 addresses testability of RTL data paths using BIST [139, 140, 144]. A new BIST methodology based on test compatibility classes achieves an improvement in terms of test application time, BIST area...
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BibTeX entry: (Update)
N. Nicolici, B.M. Al-Hashimi, A.D. Brown, and A.C. Williams. BIST hardware synthesis for RTL data paths based on test compatibility classes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(11), November 2000. http://citeseer.ist.psu.edu/nicolici00bist.html More
@misc{ nicolici00bist,
author = "N. Nicolici and B. Al-Hashimi and A. Brown and A. Williams",
title = "BIST hardware synthesis for RTL data paths based on test compatibility
classes",
text = "N. Nicolici, B.M. Al-Hashimi, A.D. Brown, and A.C. Williams. BIST hardware
synthesis for RTL data paths based on test compatibility classes. IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, 19(11), November
2000.",
year = "2000",
url = "citeseer.ist.psu.edu/nicolici00bist.html" }
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