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Abstract: In this paper we present a synthesis method that utilizes timing constraints to generate timed asynchronous circuits. By unfolding the cyclic graph specification of an asynchronous circuit into an infinite acyclic graph, we are able to use efficient algorithms to analyze the given timing constraints. We derive a sufficient condition for the removal of redundancy in the specification. Based on this condition, we only need to analyze a finite subgraph of the infinite acyclic graph for derivation... (Update)
Context of citations to this paper: More
.... benefits of improved system performance, avoidance of clocking problems, low power operation, and modular design [8, 17, 18, 14, 26, 19, 21, 28, 2, 12, 15, 6, 27, 1]. However, the design of correct asynchronous circuitry is a difficult task since an asynchronous circuit can...
...circuits that take full advantage of the fact that physical delays are always bounded. Although some work in this area has been done ([38]) a more aggressive or and more ecient optimization is still needed. Moreover, a good design ow needs an abstraction mechanism, and...
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Direct Synthesis of Timed Circuits from Free-Choice STGs - Jung, Myers (2001) (Correct)
Improved POSET Timing Analysis in Timed Petri Nets - Eric Mercer University (2001) (Correct)
Lazy Transition Systems and Asynchronous Circuit.. - Cortadella.. (2002) (Correct)
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0.2: Timing Analysis of Concurrent Systems - An Algorithm (1992) (Correct)
0.2: Synthesis of Timed Asynchronous Circuits - Chris Myers (1993) (Correct)
0.2: Interface Timing Verification with Application to Synthesis - Walkup, Borriello (1994) (Correct)
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0.5: Direct Synthesis of Timed Asynchronous Circuits - Jung, Myers (Correct)
0.4: Reference list. ICCAD'95 tutorial "The Systematic Design of. .. - Kishinevsky, al. (Correct)
0.4: Sufficient Conditions for Correct Gate-Level.. - Beerel, Burch, Meng (1994) (Correct)
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38: Performance analysis and optimization of asynchronous circuits - Burns - 1991
29: Programming in VLSI: From communicating processes to delay-insensitive VLSI circ.. (context) - Martin - 1990
27: The Post Office experience: Designing a large asynchronous chip - Coates, Davis et al. - 1993
BibTeX entry: (Update)
C. Myers and T. H.-Y. Meng. Synthesis of timed asynchronous circuits. IEEE Transactions on VLSI Systems, 1(2):106--119, June 1993. http://citeseer.ist.psu.edu/myers93synthesis.html More
@inproceedings{ myers92synthesis,
author = "Chris Myers and Teresa H.-Y. Meng",
title = "Synthesis of Timed Asynchronous Circuits",
booktitle = "Proc. International Conf. Computer Design ({ICCD})",
publisher = "IEEE Computer Society Press",
pages = "279--282",
year = "1992",
url = "citeseer.ist.psu.edu/myers93synthesis.html" }
Citations (may not include all citations):105 Performance Analysis and Optimization of Asynchronous Circui.. - Burns - 1991
80 The Design of an Asynchronous Microprocessor (context) - Martin, Bums et al. - 1989
33 Synthesis and Optimization of Interface Transducer Logic (context) - Borriello, Katz - 1987
21 Specification and Analysis of Timing Constraints in Signal T.. (context) - Vanbekbergen, Goossens et al. - 1992
14 Synthesis of Verifiably Hazard-Free Asynchronous Control Cir.. - Lavagno, Keutzers et al. - 1990
6 Algorithms for Interface Timing Verification (context) - McMillan, Dill - 1992
1 An Asynchronous Memory Management Unit (context) - Myers, Martin
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.async.elen.utah.edu/publications.html): More
Verification of Delayed-Reset Domino Circuits Using ATACS - Belluomini, Myers, Hofstee (1999) (Correct)
Covering Conditions and Algorithms for the Synthesis of.. - Beerel, Myers, Meng (1998) (Correct)
Stochastic Cycle Period Analysis in Timed Circuits - Mercer (1999) (Correct)
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