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Abstract: One of the challenges in designing systems is adopting a design method with compositional properties. Compositional functionality guarantees that two components that each perform a task can be integrated without affecting the semantics of either task. Compositional performance means that two components can be integrated so that the timing of neither components changes. In this paper we describe the hardware and software needed in order to build cache memories that have those compositional... (Update)
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BibTeX entry: (Update)
H. Muller, D. Page, J. Irwin, and D. May. Caches with compositional performance. Proc. Embedded Processor Design Challenges, pages 242--259, 2002. http://citeseer.ist.psu.edu/muller02caches.html More
@inproceedings{ muller02caches,
author = "Henk L. Muller and Dan Page and James Irwin and David May",
title = "Caches with Compositional Performance",
booktitle = "Embedded Processor Design Challenges",
pages = "242--259",
year = "2002",
url = "citeseer.ist.psu.edu/muller02caches.html" }
Citations (may not include all citations):
443
Improving Direct-Mapped Cache Performance by the Addition of..
- Jouppi - 1990
127
A Multithreaded Massively Parallel Architecture (context) - Nikhil, Papadopoulos - 1992
110
The LivermoreFortran Kernels: A Computer Test Of The Numeric.. (context) - McMahon - 1986
99
Occam-2 Reference Manual (context) - Ltd - 1988
94
Stride Directed Prefetching in Scalar Processors (context) - Fu, Patel et al. - 1992
60
Impulse: Building a Smarter Memory Controller
- Carter, Hseih et al. - 1999
42
Strategic Memory Allocation for Real-Time# Cache Design (context) - Kirk - 1989
33
Parallel MIMD Computation: The HEP Supercomputer and its App.. (context) - Kowalik - 1985
23
Compiler Support for Software-Based Cache Partitioning
- Mueller - 1995
18
A Comparative Study of Set Associative Memory Mapping Algori.. (context) - Smith - 1978
6
Compiler-Controlled Cache Mapping Rules
- Wagner
5
Bounding Instruction Cache Performance (context) - Arnold - 1996
4
Dynamic Cache Splitting
- Juan, Royo et al. - 1995
2
Systems With Predictable Caching (context) - Irwin - 2001
2
ective Use of Partitioned Cache Memories (context) - Page - 2001
2
Patent Number WO (context) - May, Muller - 2000
1
Report on the Porgramming Language Haskell (context) - Peterson, Hammond - 1996
1
Secondary Cache Data Prefetching for Multiprocessors (context) - Ki, Knowles - 1997
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