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Abstract: We evaluate the performance impact of two different write--buffer configurations (one word per buffer entry and one block per buffer entry) and two different write--policies (write--through and write--back), when using the partial block invalidation coherence mechanism [3] in a shared--memory multiprocessor. Using an execution--driven simulator, we find that the one word per entry buffer configuration with a write--back policy is preferred for small write--buffer sizes when both buffers have an ... (Update)
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BibTeX entry: (Update)
@inproceedings{ mounestoussiwrite,
author = "F. Mounes-Toussi and D. J. Lilja",
title = "Write Buffer Design for Cache-Coherent Shared-Memory Multiprocessors",
pages = "506--511",
url = "citeseer.ist.psu.edu/mounes-toussi95write.html" }
Citations (may not include all citations):496 SPLASH: Stanford Parallel Applications for Shared--Memory (context) - Singh, Weber et al. - 1992
92 Performance evaluation of memory consistency models for shar.. - Gharachorloo, Gupta et al. - 1991
65 Eliminating false sharing (context) - Eggers, Jeremiassen - 1991
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3 International Symposium on Computer Architecture (context) - Dubois, Scheurich et al. - 1986
3 Write buffer design for on--chip cache (context) - Chu, Gottipati - 1994
3 International Symposium on Computer Architecture (context) - Jouppi, policies - 1993
3 Eliminating useless messages in write--update protocols on s.. - Bianchini, LeBlanc et al. - 1994
1 A write-- through cache coherence mechanism with partially v.. (context) - Mounes-Toussi, Lilja - 1994
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