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Abstract: In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instruction fetch stage instead of the decode stage, and the mechanism is designed to operate in parallel with the tag match logic used by most cache designs. It is estimated that the critical path of the mechanism requires approximately the same number of logic levels as the tag match logic, and therefore should not impact... (Update)
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BibTeX entry: (Update)
M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of the 26th International Symposium on Microarchitecture (MICRO 26), pages 202--213, Austin, TX, December 1993. http://citeseer.ist.psu.edu/moudgill93register.html More
@techreport{ moudgill93register,
author = "Mayan Moudgill and Keshav Pingali and Stamatis Vassiliadis",
title = "Register Renaming and Dynamic Speculation: an Alternative Approach",
number = "TR93-1379",
pages = "32",
year = "1993",
url = "citeseer.ist.psu.edu/moudgill93register.html" }
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