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Mechanically Verified Hardware Implementing an 8-Bit Parallel IO Byzantine Agreement Processor (1992)  (Make Corrections)  (9 citations)
J. Strother Moore



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Abstract: Consider a network of four processors that use the Oral Messages (Byzantine Generals) algorithm of Pease, Shostak and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, Shostak and Lamport work, Bevier and Young... (Update)

Context of citations to this paper:   More

.... undertaken and completed in the following systems: EHDM and later in PVS at SRI [55, 50, 59] Nqthm, the Boyer Moore prover, at CLI [1, 2, 45, 44, 68]; and Clio and the Penelope Ada verification system at ORA [61, 4, 63, 30, 62] Concurrently we gained experience at Langley...

.... the application of mechanical theorem provers to the verification of hardware components realizing faulttolerant algorithms [22, 1, 13]. The difficulty with these verified components is that each proof involves simplifying assumptions concerning the rest of the...

Cited by:   More
A Formal Model of Asynchronous Communication and Its Use in.. - Moore (1992)   (Correct)
Comparing Verification Systems: Interactive Consistency in ACL2 - Young (1997)   (Correct)
Interaction of Formal Design Systems in the Development.. - Miner, Pullela, Johnson (1994)   (Correct)

Active bibliography (related documents):   More   All
0.2:   A Transformational Approach to Formal Digital System Design - Larsson (1993)   (Correct)
0.1:   The Role of Automated Reasoning in Integrated System.. - Good, Kaufmann, Moore (1992)   (Correct)
0.1:   NASA Langley's Research and Technology-Transfer.. - Butler, Caldwell, .. (1995)   (Correct)

Similar documents based on text:   More   All
0.5:   Formal Verification of an Oral Messages Algorithm for Interactive .. - Rushby (1992)   (Correct)
0.5:   The Proof of Correctness of a Fault-Tolerant Circuit Design - Bevier, Young (1991)   (Correct)
0.4:   A Formal HDL and its Use in the FM9001 Verification - Hunt, Jr., Brock (1992)   (Correct)

Related documents from co-citation:   More   All
6:   The proof of correctness of a fault-tolerant circuit design - Bevier, Young - 1991
5:   Verifying the interactive convergence clock synchronization algorithm using the .. - Young - 1992
5:   A Computational Logic Handbook (context) - Boyer, Moore - 1988

BibTeX entry:   (Update)

J Strother Moore, "Mechanically verified hardware implementing an 8-bit parallel io byzantine agreement processor", NASA CR-189588, Apr. 1992. http://citeseer.ist.psu.edu/moore92mechanically.html   More

@misc{ moore92mechanically,
  author = "J. Moore",
  title = "Mechanically verified hardware implementing an 8-bit parallel io byzantine
    agreement processor",
  text = "J Strother Moore, Mechanically verified hardware implementing an 8-bit
    parallel io byzantine agreement processor, NASA CR-189588, Apr. 1992.",
  year = "1992",
  url = "citeseer.ist.psu.edu/moore92mechanically.html" }
Citations (may not include all citations):
334   A Computational Logic Handbook (context) - Boyer, Moore - 1988  ACM
256   Reaching Agreement in the Presence of Faults (context) - Pease, Shostak et al. - 1980  ACM   DBLP
19   A Formal Model of Asynchronous Communication and Its Use in .. - Moore - 1992
14   The Proof of Correctness of a Fault-Tolerant Circuit Design - Bevier, Young - 1991
14   Formal Verification of the Interactive Convergence Clock Syn.. - Rushby, von Henke - 1989
4   A Formal Introduction to a Simple HDL (context) - Brock, Hunt - 1990
1   Hardware Description Language (context) - Thomas, Moorby - 1991



The graph only includes citing articles where the year of publication is known.


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