Timing model extraction of hierarchical blocks by graph reduction (2002) [2 citations — 0 self]
Abstract:
Timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from gate-level netlist by reducing a timing graph. Previous methods of generating timing models sacrificed accuracy and/or did not scale well with design size. The proposed method is simple, yet it provides model accuracy including arbitrary levels of latch time borrowing, correct support for self-loop timing checks and capability to support timing constraints that span multiple blocks. Also, cpu and memory resources required to generate the model scale well with size of the circuit. We were able to extract a model for a 456K gate block using under 2 minutes of cpu time and 464 MB of memory on a Sun Fire 880 machine. The generated model can provide a capacity improvement in timing verification by more than two orders of magnitude. 1.
Citations
| 13 | Andrew R.Conn, “Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and Redundancy by Timing Graph Manipulation – Visweswariah - 1999 |
| 2 | Extracting accurate and efficient timing models of latch-based designs – Segal - 1998 |
| 1 | A CMOS Timing Analyzer, Design Automation Conference – Cherry - 1988 |
| 1 | A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models – McDonald, Bryant |
