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Abstract: this paper, we introduce these power management techniques in behavioral synthesis. We present a scheduling algorithm which maximizes the "shut-down" period of execution units in a system. Given a throughput constraint and the number of execution units available, the algorithm first schedules operations that generate controlling signals and activates only those modules whose result is eventually used. We present results which show that this scheduling technique can save up to 40% in power... (Update)
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BibTeX entry: (Update)
J. Monteiro, P. Ashar, and S. Devadas, "Scheduling techniques to enable powermanagement,"in Proc. Design Automation Conf.,pp. 349-- 352, June 1996. http://citeseer.ist.psu.edu/monteiro96scheduling.html More
@inproceedings{ monteiro96scheduling,
author = "Jose Monteiro and Srinivas Devadas and Pranav Ashar and Ashutosh Mauskar",
title = "Scheduling Techniques to Enable Power Management",
booktitle = "Design Automation Conference",
pages = "349-352",
year = "1996",
url = "citeseer.ist.psu.edu/monteiro96scheduling.html" }
Citations (may not include all citations):114 Fast Prototyping of Datapath-Intensive Architectures (context) - Rabaey, Chu et al. - 1991
68 Precomputation-Based Sequential Logic Optimization for Low P.. - Alidina, Monteiro et al. - 1994
52 HYPER-LP: A System for Power Minimization Using Architectura.. (context) - Chandrakasan, Potkonjak et al. - 1992
52 Behavioral Synthesis for Low Power (context) - Raghunathan, Jha - 1994
41 Guarded evaluation Pushing power management to logic synthes.. - Ashar, evaluation et al. - 1995
23 A High-level Language and Silicon Compiler for Digital Signa.. (context) - Hilfinger - 1985
7 Optimization of Combinational and Sequential Logic Circuits .. - Monteiro, Rinderknecht et al. - 1995
3 Condition Graphs for HighQuality Behvioral Synthesis (context) - Juan, Chaiyakul et al. - 1994
2 Low Power Digital CMOS Design (context) - Chandrakasan, Brodersen - 1995
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