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Abstract: Switching activity is the primary cause of power dissipation in CMOS combinational and sequential circuits. We give a method of estimating power in pipelined sequential CMOS circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. (Update)
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BibTeX entry: (Update)
J. Monteiro, S. Devadas, and A. Ghosh. Retiming Sequential Circuits for Low Power. In Proceedings of the Int'l Conference on Computer-Aided Design, pages 398--402, November 1993. http://citeseer.ist.psu.edu/monteiro93retiming.html More
@inproceedings{ monteiroretiming,
author = "J. Monteiro and S. Devadas and A. Ghosh",
title = "Retiming Sequential Circuits for Low Power",
pages = "398--402",
url = "citeseer.ist.psu.edu/monteiro93retiming.html" }
Citations (may not include all citations):296 Low Power CMOS Digital Design - Chandrakasan, Sheng et al. - 1992
158 Estimation of Average Switching Activity in Combinational an.. - Ghosh, Devadas et al. - 1992 ACM DBLP
80 On Average Power Dissipation and Random Pattern Testability .. (context) - Shen, Devadas et al. - 1992
80 Optimizing Synchronous Circuitry by Retiming (context) - Leiserson, Rose et al. - 1983
37 A Stochastic Measure of Activity in Digital Circuits (context) - Najm - 1991
4 Low-Power DSP Circuit Design Using Retimed Maximally Paralle.. (context) - Duncan, Swamy et al. - 1993
4 Computer Science Press (context) - Kohavi, Finite - 1978
2 IEEE Transactions on Computer Aided Design (context) - De Micheli, Synthesis - 1991
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