by Carlos Molina, Jordi Tubella
International Conference on Supercomputing
ftp://ftp.ac.upc.es/pub/reports/DAC/1998/UPC-DAC-1998-22.ps.Z
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Abstract:
A mechanism for dynamic instruction-level reuse in superscalar microprocessors is presented. The underlying concept that the mechanism exploits is the run-time removal of redundant computations, and in particular the elimination of common subexpressions and invariants. Removing redundant computation is a target of optimizing compilers but sometimes they do not succeed due to their limited knowledge of the data. Moreover, the proposed mechanism can also remove quasi-redundant computations, such as subexpressions that often produce the same result but sometimes they differ, depending on the data values, and thus they cannot be eliminated by the compiler. Experimental results for the Spec95 show that on average the mechanism can avoid the execution of about 32 % of the dynamic instructions and provides a 1.10 speedup in a superscalar microprocessor. An extensive evaluation of different configurations and a comparison with previous schemes is presented, as well as the performance potential of a perfect reuse engine.
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