Tushar Mohan, Bronis R. de Supinski, Sally A. McKee, Frank Mueller, Andy Yoo, Martin Schulz  Home/Search
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Abstract: The growing processor/memory performance gap causes the performance of many codes to be limited by memory accesses. If known to exist in an application, strided memory accesses forming streams can be targeted by optimizations such as prefetching, relocation, remapping, and vector loads. Undetected, they can be a significant source of memory stalls in loops. Existing stream-detection mechanisms either require special hardware, which may not gather statistics for subsequent analysis, or are... (Update)
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BibTeX entry: (Update)
@misc{ mohan-identifying,
author = "Tushar Mohan and Bronis R. de Supinski and Sally A. McKee and Frank Mueller
and Andy Yoo and Martin Schulz",
title = "Identifying and Exploiting Spatial Regularity in Data Memory References",
url = "citeseer.ist.psu.edu/mohan03identifying.html" }
Citations (may not include all citations):1575 Computer Architecture: A Quantitative Approach (context) - HENNESSY, PATTERSON - 1996
305 The NAS Parallel Benchmarks - BAILEY, BARSZCZ et al. - 1991
217 NASA Ames Research Center (context) - BAILEY, BISWAS et al. - 1997
162 Improving data locality with loop transformations - MCKINLEY, CARR et al. - 1996
122 An effective on-chip preloading scheme to reduce data access.. (context) - BAER, CHEN - 1991
88 Data-centric multi-level blocking - KODUKULA, AHMED et al. - 1997
78 Data prefetching in multiprocessor vector cache memories (context) - FU, PATEL - 1991
73 Cacheconscious structure layout - CHILIMBI, HILL et al. - 1999
72 Cache-conscious data placement - CALDER, CHANDRA et al. - 1998
70 Maximizing loop parallelism and improving data locality via .. - KENNEDY, MCKINLEY - 1993
68 Beyond induction variables: detecting and classifying sequen.. - GERLEK, STOLTZ et al. - 1995
60 Impulse: Building a smarter memory controller - CARTER, HSIEH et al. - 1999
57 Improving cache performance in dynamic applications through .. - DING, KENNEDY - 1999
46 An API for runtime code patching - BUCK, HOLLINGSWORTH - 2000
19 Efficient representations and abstractions for quantifying a.. - CHILIMBI - 2001
14 Locality optimizations for multi-level caches - RIVERA, TSENG - 1999
12 Code generation streaming AccesExecute mechanism (context) - DAVIDSON, for et al. - 1991
8 Near-optimal padding for removing conflict misses - VERA, LLOSA et al. - 2002
8 Dynamic access ordering for streamed computations - MCKEE, WULF et al. - 2000
4 Metric: Tracking down inefficiencies in the memory hierarchy.. - MARATHE, MUELLER - 2003
3 SIGMA: A simulator infrastructure to guide memory analysis - DEROSE, EKANADHAM et al. - 2002
2 A framework for performance modeling and prediction - SNAVELY, CARRINGTON et al. - 2002
2 RS/6000 Scientific and Technical Computing: POWER3 Introduct.. (context) - MACHINES - 1998
2 Detecting and exploiting spatial regularity in data memory r.. (context) - MOHAN - 2003
1 Lawrence Livermore National Laboratory (context) - PARKER, DE SUPINSKI et al. - 2001
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