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Abstract: Traditionally, cache coherence in multiprocessors has been maintained in hardware. However, the cost-effectiveness of hardwired protocols is questionable. Virtual Shared Memory systems have highlighted the many advantages of software-implemented protocols, albeit at a performance price. The performance gap is narrowed by hybrid systems with the addition of hardware support for fine-grain sharing. We have developed a software protocol for a COMA (Cache-Only Memory Architecture) on a distributed... (Update)
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...and its block size is 128 bytes. The page size is 4 KB for all simulations. The timing and network model are the same as in [21]. An FLC hit has no latency charge and an SLC hit takes 6 cycles. A hit in attraction memory takes 74 cycles. The network is an 8 bit wide...
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BibTeX entry: (Update)
Adrian Moga, Alain Gefflaut, and Michel Dubois, "Hardware vs. Software Implementation of COMA", In Proceedings of the 1997 Int'l Conference on Parallel Processing, pages 248-256, August 1997. http://citeseer.ist.psu.edu/moga97hardware.html More
@inproceedings{ moga97hardware,
author = "A. Moga and A. Gefflaut and M. Dubois",
title = "Hardware vs. Software Implementation of {COMA}: {A} Performance Comparison",
booktitle = "Proc. of the 1997 Int'l Conf. on Parallel Processing ({ICPP}'97)",
year = "1997",
url = "citeseer.ist.psu.edu/moga97hardware.html" }
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