Design, Analysis and Implementation of an Adder (1994)
by Manfred Minimair
ftp://ftp.risc.uni-linz.ac.at/pub/techreports/1995/95-15.ps.gz
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Abstract:
An addition circuit by Ladner and Fisher is analysed. It has size bounded by (8+6 \Delta 2 \Gammak)n and depth bounded by 2dlog 2 ne+2k+2, where 0 k dlog 2 ne and n is the bit length of the input numbers. Moreover the implementation of an instance of this adder capable of adding two numbers of 8-bit length was timed. The average computing time of its logical design and its layout is 26:8 ns and 94:2 ns, respectively. The layout of this circuit was done on an
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