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Abstract: In this paper we propose a design strategy that exploits the strengths of different formal approaches to establish a reliable path from a mechanically verified high-level description to a concrete gate-level realization. We demonstrate the use of this approach in the realization of a fault-tolerant clock synchronization circuit. We used the Digital Design Derivation system (DDD) to derive major portion of the design leaving relatively small portions to be verified either by use of a mechanical... (Update)
Context of citations to this paper: More
.... and engineers gain design experience in a formal framework, both approaches are emerging as interdependent facets of design [44, 8, 54]. The thesis of this work is that alternate forms of formal reasoning must be integrated if formal methods are to support the natural...
.... colleagues at Indiana University later developed and implemented a verified clock synchronization circuit that implements this algorithm [36]. Several formal methods were used in their design and implementation. The register transfer level architecture was developed using the...
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BibTeX entry: (Update)
Paul S. Miner, Shyamsundar Pullela, and Steven D. Johnson, "Interaction of formal design systems in the development of a fault-tolerant clock synchronization circuit", in 13th Symposium on Reliable Distributed Systems, pp. 128-- 137, Dana Point, California, October 1994. http://citeseer.ist.psu.edu/miner94interaction.html More
@inproceedings{ miner94interaction,
author = "Paul S. Miner and Shyamsundar Pullela and Steven D. Johnson",
title = "Interaction of Formal Design Systems in the Development of a Fault-Tolerant Clock Synchronization Circuit",
booktitle = "Symposium on Reliable Distributed Systems",
pages = "128-137",
year = "1994",
url = "citeseer.ist.psu.edu/miner94interaction.html" }
Citations (may not include all citations):510 Symbolic boolean manipulation with ordered binary decision d.. - Bryant - 1992 ACM
295 PVS: A prototype verification system (context) - Owre, Rushby et al. - 1992 DBLP
85 Optimal clock synchronization - Srikanth, Toueg - 1987 ACM DBLP
84 A new fault-tolerant algorithm for clock synchronization - Welch, Lynch - 1988 ACM DBLP
74 Understanding protocols for Byzantine clock synchronization - Schneider - 1987 ACM
44 A formally verified algorithm for interactive consistency un.. - Lincoln, Rushby - 1993 ACM DBLP
33 A formal HDL and its use in the FM9001 verification - Hunt - 1992 ACM
26 Verification of fault-tolerant clock synchronization systems (context) - Miner - 1993 ACM
25 An introduction to formal specification and verification usi.. - Rushby, von Henke et al. - 1991
24 Mechanical verification of a generalized protocol for byzant.. - Shankar - 1992
23 Using transformations and verification in circuit design (context) - Saxe, Garland et al. - 1991 ACM DBLP
20 DDD - A Transformation system for Digital Design Derivation (context) - Bose - 1991
18 DDD-FM9001: Derivation of a verified microprocessor - Bose, Johnson - 1993 DBLP
14 The proof of correctness of a fault-tolerant circuit design - Bevier, Young - 1991
12 A tactical framework for digital design (context) - Johnson, Bose et al. - 1988
11 High level design proof of a reliable computing platform - Di Vito, Butler et al. - 1992 ACM
11 Verification of the FtCayuga fault-tolerant microprocessor s.. (context) - Srivas, Bickford - 1991
10 The Art of Digital Design (context) - Prosser, Winkel - 1987
9 the interplay of synthesis and verification: Experiments wit.. (context) - Johnson, Wehrmeister et al. - 1989
9 Mechanically verified hardware implementing an 8-bit paralle.. - Moore - 1992 ACM
6 Provable transient recovery for frame-based (context) - Di Vito, Butler - 1992
6 Integrating boolean verification with formal derivation - Bose, Johnson et al. - 1993 ACM DBLP
5 Continuations in hardware-software codesign - Tuna, Johnson et al. - 1994 ACM DBLP
4 Moving formal methods into practice: Verifying the FTPP scor.. (context) - Srivas, Bickford - 1992
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