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Abstract: this paper, we first present an overview of the various architecture synthesis tasks and analyze their influence on power consumption. A survey of previously proposed techniques is given, and areas of opportunity are identified. We next propose a new architecture synthesis technique for low-power implementation of real-time applications. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. Preserving locality results in more compact... (Update)
Context of citations to this paper: More
.... power consumption in interconnect elements by exploiting locality of reference minimizing the accesses over global computing resources [8]. Srivastava, et al. performed a demand driven operation and predictive powerdown to avoid wasteful transitions [9] Abnous and Rabaey...
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BibTeX entry: (Update)
Renu Mehra, Lisa M. Guerra, and Jan M. Rabaey, "Lowpower architectural synthesis and the impact of exploiting locality," Journal of VLSI Signal Processing, vol. 13, pp. 239--258, 1996. http://citeseer.ist.psu.edu/mehra96lowpower.html More
@misc{ mehra96lowpower,
author = "R. Mehra and L. Guerra and J. Rabaey",
title = "Lowpower architectural synthesis and the impact of exploiting locality",
text = "Renu Mehra, Lisa M. Guerra, and Jan M. Rabaey, Lowpower architectural synthesis
and the impact of exploiting locality, Journal of VLSI Signal Processing,
vol. 13, pp. 239--258, 1996.",
year = "1996",
url = "citeseer.ist.psu.edu/mehra96lowpower.html" }
Citations (may not include all citations):1527 Optimization by Simulated Annealing - Kirkpatrick, Gelatt et al. - 1983 ACM
429 An Efficient Heuristic Procedure for Partitioning Graphs (context) - Kernighan, Lin - 1970
421 A Linear-time Heuristic for Improving Network Partitions (context) - Fiduccia, Matteyses - 1982 ACM
264 Combinatorial Algorithms for Integrated Circuit Layout (context) - Lengauer - 1990 ACM
219 Partitioning of Unstructured Problems for Parallel Processin.. - Simon - 1991
217 High-Level Synthesis: Introduction to Chip and System Design (context) - Gajski - 1992
151 Force-Directed Scheduling for Behavioral Synthesis of ASIC's (context) - Paulin, Knight - 1989
114 Fast Prototyping of Datapath-Intensive Architectures (context) - Rabaey, Chu et al. - 1991 ACM
107 Optimizing Power Using Transformations - Chandrakasan, Potkonjak et al. - 1995
73 New Spectral Methods for Ratio Cut Partitioning and Clusteri.. (context) - Hagen, Kahng - 1992
68 Short-Circuit Dissipation of Static CMOS Circuitry and its I.. (context) - Veendrick - 1984
65 Architectural Power Analysis: The Dual Bit Type Method (context) - Landman, Rabaey - 1995
61 Ratio Cut Partitioning for Hierarchical Designs (context) - Wei, Cheng - 1991
57 An Algorithm for Partitioning the Nodes of a Graph (context) - Barnes - 1994
52 Behavioral Synthesis for Low-Power (context) - Raghunathan, Jha - 1994
50 Global Communication and Memory Optimizing Transformations f.. - Catthoor, Franssen et al. - 1994
44 A Survey of High Level Synthesis Systems (context) - Walker, Camposano - 1991
39 Architectural Partitioning for System Level Synthesis of Int.. (context) - Lagnese, Thomas - 1991
36 Kluwer Academic Publishers (context) - Brodersen, of et al. - 1992
36 Behavioral Level Power Estimation and Exploration - Mehra, Rabaey - 1994
34 An r-Dimensional Quadratic Placement Algorithm (context) - Hall - 1970
30 Spectral K-way Ratio-cut Partitioning and Clustering (context) - Chan, Schlag et al. - 1994
27 Incorporating Bottom-up Design into Hardware Synthesis (context) - McFarland, Kowalski
27 Geometric Embeddings for Faster and Better Multi-Way Netlist.. - Alpert, Kahng - 1993 ACM DBLP
25 Logic Partitioning (context) - Donath - 1988 ACM
25 A Proper Model for the Partitioning of Electrical Circuits (context) - Schweikert, Kernighan - 1972 ACM
21 Register Allocation and Binding for Low Power - Chang, Pedram - 1995 ACM DBLP
21 High-Level Synthesis Techniques for Reducing the Activity of.. - Musoll, Cortadella - 1995 ACM
19 An Iterative Improvement Algorithm for Low Power Data Path S.. - Raghunathan, Jha - 1995 ACM
15 Circuit Placement and Cost Bounds by Eigenvector Decompositi.. (context) - Frankle, Karp - 1986
15 Microarchitectural Synthesis of Performance Constrained, Low.. (context) - Goodby, Orailoglu et al. - 1994
11 Memory Segmentation to Exploit Sleep Mode Operation (context) - Farrahi, Tellez et al. - 1995 ACM DBLP
9 Synthesis of Low Power Linear DSP Circuits using Activity Me.. (context) - Chatterjee, Roy - 1994 DBLP
5 Impact of CAD on the Design of Low Power Digital Circuits - Keutzer, Vanbekbergen - 1994
4 Partitioning Logic on Graph Structures to Minimize Routing C.. (context) - Vijayan - 1990
3 A Hardware Library Representation for the Hyper Synthesis Sy.. (context) - Wu - 1994
2 The Chaco User's Guide, V. 1.0 (context) - Hendrickson, Leland - 1993
2 Scheduling Algorithms for Hierarchical Data Control Flow Gra.. (context) - Potkonjak, Rabaey - 1992
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